User-programmable, integrated circuits (ICs) e.g. Field Programmable Gate Arrays (FPGAs) are increasingly popular for embedded, high-performance data exploitation. They combine the parallelization capability and processing power of application specific integrated circuits (ASICs) with the exibility, scalability and adaptability of software-based processing solutions. FPGAs provide powerful processing resources due to an optimal adaptation to the target application and a well-balanced ratio of performance, efficiency and parallelization. One drawback of FPGA-based data exploitation is the limited memory capacity of reconfigurable integrated circuits. Large-scale Digital Signal Processor (DSP) FPGAs provide approximately 4MB on-board random access memory (RAM) which is not sufficient to buffer the broadband sensor and result data. Hence, additional external memory is connected to the FPGA to increase on-board storage capacities. External memory devices like double data rate three synchronous dynamic random access memories (DDR3-SDRAM) provide very fast and wide bandwidth interfaces that represent a bottleneck when used in highly parallelized processing architectures. Independent processing modules are demanding concurrent read and write access. Within the master thesis, a concept for the integration of an external DDR3- SDRAM into an FPGA-based parallelized processing architecture is developed and implemented. The solution realizes time division multiple access (TDMA) to the external memory and virtual, low-latency memory extension to the on-board buffer capabilities. The integration of the external RAM does not change the way how on-board buffers are used (control, data-fow).

Submitted by JOSIANE SANTOS DE OLIVEIRA (josianeso) on 2017-10-25T13:48:51Z No. of bitstreams: 1 Samuel Lessinger_.pdf: 3503378 bytes, checksum: 92c0e6ccfb6dfb145bc9a84b3ce1ceed (MD5) / Made available in DSpace on 2017-10-25T13:48:52Z (GMT). No. of bitstreams: 1 Samuel Lessinger_.pdf: 3503378 bytes, checksum: 92c0e6ccfb6dfb145bc9a84b3ce1ceed (MD5) Previous issue date: 2017-09-21 / PADIS - Programa de apoio ao desenvolvimento tecnológico da indústria de semicondutores / O presente trabalho consiste em uma proposta de uma plataforma reconfigurável para testes de módulos de memória SDRAM DDR3. Testadores de módulos de memória consistem em sistemas de arquiteturas fechadas, nos quais o usuário possui pouca flexibilidade em sua utilização, transporte e são na maioria das vezes sistemas volumosos próprios para uso em bancadas. Neste cenário, uma plataforma portátil de baixo custo, que possibilite ao usuário descrever os algoritmos de teste torna-se interessante. A plataforma desenvolvida utiliza de Field Programmable Gate Arrays (FPGA) o que proporciona a característica de reconfiguração. Neste projeto foi proposta e validada uma estratégia de injeção de falhas do tipo Stuck-At-Zero, aliado a um sistema automático para coleta de vetores de teste e para a síntese em diferentes frequências de acesso aos módulos de memória. A etapa de validação do protótipo desenvolvido possibilitou reportar a captura de 131.751 falhas, graças ao framework criado para acompanhar a tarefa de injeção de falhas. / This work consists on a proposal of a DDR3 SDRAM memory module reconfigurable test platform. Memory module testers are usually closed architecture systems, in which the user has little flexibility in their use. In this scenario, a low-cost portable platform, which enables the user to describe his own test algorithm becomes interesting. This work explores the use of Field Programmable Gate Arrays (FPGAs) in order to construct a fully reconfigurable testing platform. In this work a Stuck-At-Zero fault injection strategy was proposed and validated. Results report the success in executing fault detection algorithms as well as the software framework developed for the fault injection campaign.

Goal of the diploma thesis is a design of fast memory module and to introduce myself with issues involved in data storage in memory of high speed camera. The work is concerned about two designs adding memory capacity of high speed camera with DDR3 memory modules. For production is selected the more suitable design that is better for commercial purposes. The main objective is to design a schematic with FPGA as a main controller, that will operate data flow from CMOS sensor to superior development board MicroZed. Final design should allow us to sell the high speed camera as a separate unit.

User-programmable, integrated circuits (ICs) e.g. Field Programmable Gate Arrays (FPGAs) are increasingly popular for embedded, high-performance data exploitation. They combine the parallelization capability and processing power of application specific integrated circuits (ASICs) with the exibility, scalability and adaptability of software-based processing solutions. FPGAs provide powerful processing resources due to an optimal adaptation to the target application and a well-balanced ratio of performance, efficiency and parallelization. One drawback of FPGA-based data exploitation is the limited memory capacity of reconfigurable integrated circuits. Large-scale Digital Signal Processor (DSP) FPGAs provide approximately 4MB on-board random access memory (RAM) which is not sufficient to buffer the broadband sensor and result data. Hence, additional external memory is connected to the FPGA to increase on-board storage capacities. External memory devices like double data rate three synchronous dynamic random access memories (DDR3-SDRAM) provide very fast and wide bandwidth interfaces that represent a bottleneck when used in highly parallelized processing architectures. Independent processing modules are demanding concurrent read and write access. Within the master thesis, a concept for the integration of an external DDR3- SDRAM into an FPGA-based parallelized processing architecture is developed and implemented. The solution realizes time division multiple access (TDMA) to the external memory and virtual, low-latency memory extension to the on-board buffer capabilities. The integration of the external RAM does not change the way how on-board buffers are used (control, data-fow).