From the initial implementations for the DEC PDP-11 to those of today done for commodity PICs, the TCP/IP code stack continues to work its way into a smaller and more omnipresent class of devices. One shortcoming of current devices on the leading edge of this trend is that they belong more to the microcontroller categories, which typically lack any appreciable signal processing capability. Applications such as consumer electronics and wireless sensor networks could benefit greatly from single-chip network-capable devices which are based on a Digital Signal Processing (DSP) core rather than a microcontroller. This report details the design and implementation of a partial TCP/IP code stack intended for such a DSP. / text

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Finite-length impulse response (FIR) filters are one of the most commonly used digital signal processing algorithms used nowadays where a FPGA is the device used to implement it. The continued development of the FPGA device through the insertion of dedicated blocks raised the need to study the advantages offered by different FPGA families. The work presented in this thesis study the special features offered by FPGAs for FIR filters and introduce a cost model of resource utilization. The used method consist of several stages including reading, classification of features and generating coefficients. The results show that FPGAs have common features but also specific differences in features as well as resource utilization. It has been shown that there is misconception when dealing with FPGAs when it comes to FIR filter as compared to ASICs.

This paper describes the design of an inexpensive UHF transceiver which leverages some of the recently developed commercial off-the-shelf (COTS) components. The initial goal is to implement digital voice transmit and receive function, although the design can accommodate a wide range of digital communication and telemetry applications. The handheld transceiver transmits 5 watts of power in the 430-435 MHz UHF band. A 1.2 kHz wide GFSK modulation format is used, generated by a Silicon Labs radio chip. The recently released Raspberry Pi Zero processor implements a low bit rate audio coding which conforms to the Codec2 standard. The transceiver fits in a 3 cm x 8 cm x 14 cm volume. It is powered by two 18650 lithium ion cells, and draws approximately 1 watt of power during receive, and 6 watts during transmission.

Until now, the performance improvement of computing machines was a mostly a result of shrinking transistor geometries and increasing clock speeds. With the advent of signal processing applications that have stringent performance requirements from processing hardware, the field of configurable computing has received a lot of attention. Efforts are being made to improve computation bandwidth by architectural innovations. Among these, the wormhole runtime reconfigurable architecture introduces the concept of stream processing. It enables dynamic reconfiguration of hardware with little overheads and is very much suited for data-path based computations with deep computational pipelines. Stallion, second in the generation of Wormhole runtime reconfigurable processors, demonstrates the efficacy of wormhole runtime reconfiguration. The work presented here deals with the VLSI implementation of Stallion and discusses the full-custom physical design flow adopted for Stallion. Also, the tools and techniques to customize this flow are detailed. The Stallion design methodology offers a possible solution that can be pursued for executing similar efforts in future. / Master of Science

In recent years, interest in the area of custom computing machines (CCMs) has been on a steady increase. Much of the activity surrounding CCMs has centered around Field-Programmable Gate Array (FPGA) technology and rapid prototyping applications. While higher performance has been a concern in some applications, the solutions are limited by the relatively small FPGA bandwidth, density and throughput. This leads to area, speed, power, and application-specific constraints. In recent months, an integrated circuit known as the VT Colt has been developed to address some high performance digital signal processing (DSP) problems that conventional processors, CCMs, and ASICs cannot do under the space and power constraints. The Colt chip takes a data-flow approach to processing and is highly reconfigurable to suit the many computationally demanding tasks that new DSP applications present. A significant portion of the development of the Colt chip is architectural justification, functional verification, and configurability. This thesis explores verification of the Colt chip at various levels of development including mapping arithmetic computations and DSP algorithms that the Colt architecture was designed to solve. / Master of Science

Os logos de televisão são uma das mais importantes estratégias criadas e registradas pelas emissoras de televisão para proteger o conteúdo produzido e distribuído por elas. Cada logo é único, gerando robustez e segurança ao processo de medição de audiência de televisão. Estes logos podem ser considerados uma marca d\'água, que em alguns casos identificam não só a emissora, mas também o tipo de conteúdo que está sendo veiculado. Por exemplo, alguns canais mudam o logo de semitransparente para opaco quando há uma transmissão ao vivo. No reconhecimento de logos em tempo real utilizando-se sistemas embarcados, torna-se necessário o uso de técnicas que reduzam o processamento e o armazenamento de dados. Neste trabalho estudamos os principais métodos envolvidos em reconhecimento de imagens encontrados na literatura. Verificamos o uso do logo em outras aplicações, e desenvolvemos uma solução viável, técnica e economicamente. Aplicamos a técnica proposta em dados previamente gravados, e também em situações em tempo real, onde não se tem o controle do tipo de vídeo ao qual será veiculado. Avaliamos o novo método proposto e sua melhoria ao longo do processo, demonstrando a sua viabilidade. Apresentamos resultados comparativos entre o primeiro paper publicado e os novos métodos. / Television logo is one of the most important strategies used by the broadcasting companies to claim and protect the contents created and broadcasted by them. Each logo is unique, yielding robustness and security to the measurement of television audience. These logos can be considered as visible watermarks, and in some cases can identify the kind of broadcasted content, besides identifying the broadcasting company. For instance, some broadcasting company changes the logo\'s type from semitransparent to opaque to identify a live broadcast. For real time logo recognition using embedded systems, it is necessary to reduce the amount of processing and the memory storage. In this work, we describe the methods involved in logo recognition found in the literature. We verify the use of logos in other applications, and developed a technically and economically viable solution to recognize television logos in real time.

Com o crescimento acelerado da complexidade das aplicações e softwares que exigem alto desempenho, o hardware e sua arquitetura passou por algumas mudanças para que pudesse atender essa necessidade. Uma das abordagens propostas e desenvolvidas para suportar essas aplicações, foi a integração de mais de um core de processamento em um único circuito integrado. Inicialmente, a comunicação utilizando barramento foi escolhida, pela sua vantagem de reuso comparado a ponto a ponto. No entanto, com o aumento acelerado da quantidade de cores nos Systems-on-Chip (SoC), essa abordagem passou a apresentar problemas para suportar a comunicação interna. Uma alternativa que vem sendo explorada é a Network-on-Chip (NoC), uma abordagem que propõe utilizar o conhecimento de redes comuns em projetos de comunicação interna de SoC. Esse trabalho fornece uma arquitetura de NoC completa, configurável, parametrizável e no padrão Ethernet. Os três módulos básicos da NoC, Network Adapter (NA), Link e Switch, são implementados e disponibilizados. Os resultados foram obtidos utilizando o FPGA Stratix IV da Altera. As métricas de desempenho utilizadas para validação da NoC são a área no FPGA e o atraso na comunicação. Os parâmetros disponibilizados são referentes as configurações dos módulos desenvolvidos, considerando características apresentadas de aplicações DSP (Digital Signal Processing). O experimento utilizando dois NAs, dois cores e um Switch precisou de 7310 ALUTs do FPGA EP4SGX230KF40C2ES o que corresponde a 4% dos seus recursos lógicos. O tempo gasto para a transmissão de um quadro ethernet de 64 Bytes foi de 422 ciclos de clock a uma frequência de 50MHz. / With the accelerated growth of the complexity of the software and applications that require high performance, hardware and its architecture has undergone a few changes so it could meet that need. One of the proposals and approaches developed to support these applications, was the integration of more than one core processing in a single integrated circuit. Initially, the bus communication architecture was chosen, using for its reuse benefit compared to point-to-point. However, with the cores number increase in Systems-on-Chip (SoC), this approach began to present problems to support internal communication. An alternative that has been explored is the Network-on-Chip (NoC), an approach that proposes to use knowledge of common networks on internal communication projects of SOC. This dissertation focuses is to provide a complete NoC architecture, configurable, customizable and on standard Ethernet. The three NoC basic modules, Network Adapter (NA), Link and Switch, are implemented. The results were obtained using the Stratix IV FPGA. The performance metrics used for NoC validation are silicon area and latency. The available parameters are related to developed modules settings, considering features presented of DSP applications. The experiment using two NA, two cores and one Switch needed 7310 FPGA ALUTs which corresponds to 4% of their logical resources. The time for the transmission of an ethernet frame of 64 Bytes was 422 clock cycles at 50 MHz.

Os logos de televisão são uma das mais importantes estratégias criadas e registradas pelas emissoras de televisão para proteger o conteúdo produzido e distribuído por elas. Cada logo é único, gerando robustez e segurança ao processo de medição de audiência de televisão. Estes logos podem ser considerados uma marca d\'água, que em alguns casos identificam não só a emissora, mas também o tipo de conteúdo que está sendo veiculado. Por exemplo, alguns canais mudam o logo de semitransparente para opaco quando há uma transmissão ao vivo. No reconhecimento de logos em tempo real utilizando-se sistemas embarcados, torna-se necessário o uso de técnicas que reduzam o processamento e o armazenamento de dados. Neste trabalho estudamos os principais métodos envolvidos em reconhecimento de imagens encontrados na literatura. Verificamos o uso do logo em outras aplicações, e desenvolvemos uma solução viável, técnica e economicamente. Aplicamos a técnica proposta em dados previamente gravados, e também em situações em tempo real, onde não se tem o controle do tipo de vídeo ao qual será veiculado. Avaliamos o novo método proposto e sua melhoria ao longo do processo, demonstrando a sua viabilidade. Apresentamos resultados comparativos entre o primeiro paper publicado e os novos métodos. / Television logo is one of the most important strategies used by the broadcasting companies to claim and protect the contents created and broadcasted by them. Each logo is unique, yielding robustness and security to the measurement of television audience. These logos can be considered as visible watermarks, and in some cases can identify the kind of broadcasted content, besides identifying the broadcasting company. For instance, some broadcasting company changes the logo\'s type from semitransparent to opaque to identify a live broadcast. For real time logo recognition using embedded systems, it is necessary to reduce the amount of processing and the memory storage. In this work, we describe the methods involved in logo recognition found in the literature. We verify the use of logos in other applications, and developed a technically and economically viable solution to recognize television logos in real time.

Com o crescimento acelerado da complexidade das aplicações e softwares que exigem alto desempenho, o hardware e sua arquitetura passou por algumas mudanças para que pudesse atender essa necessidade. Uma das abordagens propostas e desenvolvidas para suportar essas aplicações, foi a integração de mais de um core de processamento em um único circuito integrado. Inicialmente, a comunicação utilizando barramento foi escolhida, pela sua vantagem de reuso comparado a ponto a ponto. No entanto, com o aumento acelerado da quantidade de cores nos Systems-on-Chip (SoC), essa abordagem passou a apresentar problemas para suportar a comunicação interna. Uma alternativa que vem sendo explorada é a Network-on-Chip (NoC), uma abordagem que propõe utilizar o conhecimento de redes comuns em projetos de comunicação interna de SoC. Esse trabalho fornece uma arquitetura de NoC completa, configurável, parametrizável e no padrão Ethernet. Os três módulos básicos da NoC, Network Adapter (NA), Link e Switch, são implementados e disponibilizados. Os resultados foram obtidos utilizando o FPGA Stratix IV da Altera. As métricas de desempenho utilizadas para validação da NoC são a área no FPGA e o atraso na comunicação. Os parâmetros disponibilizados são referentes as configurações dos módulos desenvolvidos, considerando características apresentadas de aplicações DSP (Digital Signal Processing). O experimento utilizando dois NAs, dois cores e um Switch precisou de 7310 ALUTs do FPGA EP4SGX230KF40C2ES o que corresponde a 4% dos seus recursos lógicos. O tempo gasto para a transmissão de um quadro ethernet de 64 Bytes foi de 422 ciclos de clock a uma frequência de 50MHz. / With the accelerated growth of the complexity of the software and applications that require high performance, hardware and its architecture has undergone a few changes so it could meet that need. One of the proposals and approaches developed to support these applications, was the integration of more than one core processing in a single integrated circuit. Initially, the bus communication architecture was chosen, using for its reuse benefit compared to point-to-point. However, with the cores number increase in Systems-on-Chip (SoC), this approach began to present problems to support internal communication. An alternative that has been explored is the Network-on-Chip (NoC), an approach that proposes to use knowledge of common networks on internal communication projects of SOC. This dissertation focuses is to provide a complete NoC architecture, configurable, customizable and on standard Ethernet. The three NoC basic modules, Network Adapter (NA), Link and Switch, are implemented. The results were obtained using the Stratix IV FPGA. The performance metrics used for NoC validation are silicon area and latency. The available parameters are related to developed modules settings, considering features presented of DSP applications. The experiment using two NA, two cores and one Switch needed 7310 FPGA ALUTs which corresponds to 4% of their logical resources. The time for the transmission of an ethernet frame of 64 Bytes was 422 clock cycles at 50 MHz.