Until now, the performance improvement of computing machines was a mostly a result of shrinking transistor geometries and increasing clock speeds. With the advent of signal processing applications that have stringent performance requirements from processing hardware, the field of configurable computing has received a lot of attention. Efforts are being made to improve computation bandwidth by architectural innovations. Among these, the wormhole runtime reconfigurable architecture introduces the concept of stream processing. It enables dynamic reconfiguration of hardware with little overheads and is very much suited for data-path based computations with deep computational pipelines. Stallion, second in the generation of Wormhole runtime reconfigurable processors, demonstrates the efficacy of wormhole runtime reconfiguration. The work presented here deals with the VLSI implementation of Stallion and discusses the full-custom physical design flow adopted for Stallion. Also, the tools and techniques to customize this flow are detailed. The Stallion design methodology offers a possible solution that can be pursued for executing similar efforts in future. / Master of Science

Mémoire numérisé par la Direction des bibliothèques de l'Université de Montréal.

Microprocessors have difficulties addressing the demands of today's high-performance embedded applications. ASICs are a good solution to the speed concerns, but their cost and time to market can make them impractical for some needs. Configurable Computing Machines (CCMs) provide a cost-effective way of creating custom components; however, oftentimes it would be better if there were a way to change the configuration of the CCM as a program is executing. An efficient way of doing this is with Runtime Reconfigurable (RTR) computing architectures. In an RTR system, one challenging problem is the assignment of operators onto the array of processing elements (PEs) in a way as to simultaneously minimize both the number of PEs used and the number of interconnections between them for each configuration. This job is automated through the use of a software program referred to as the Spatial Partitioner. The design and implementation of the Spatial Partitioner is the subject of this work. The Spatial Partitioner developed herein uses an iterative, recursive algorithm along with cluster refinement to find a reasonably efficient allocation of operators onto the target platform in a reasonable amount of time. Information about the topology of the target platform is used throughout the execution of the algorithm to ensure that the resulting solution is legal in terms of layout. / Master of Science

Předmětem této práce je polohově orientovaná analýza v kontextu optimalizace mobilních sítí. Popisuje nástroj pro odhadování základních parametrů sítě na místech s neznámými parametry sítě na základě databáze RTR NetTest. Je zde stručně představena oblast velkých dat, strojového učení a shrnutí o konceptu a funkcionalitě aplikace NetTest. Práce ukazuje a porovnává skupinu regresních metod na základě jejich komplexnosti a vhodnosti pro vytvoření map odhadovaných parametrů sítě. Po jejich důkladné 1D analýze je IDW a GPR analyzováno ve 2D a využito pro vytvoření skupiny map odhadu parametrů sítě. Je posouzena i jejich přesnost na základě referenčního měření aplikací NetTest.

Configurable computing machines (CCMs) are available as plug in cards for standard workstations. CCMs make it possible to achieve computing feats on workstations that were previously only possible with super computers. However, it is difficult to create applications for CCMs. The development environment is fragmented and complex. Compilers for CCMS are emerging but they are in their infancy and are inefficient. The difficulties of implementing run time reconfiguration (RTR) on CCMs are addressed in this thesis. Tools and techniques are introduced to simplify the development and synthesis of applications and partitions for RTR applications. A multiplexed memory port (MMP) is presented in JHDL and VHDL that simplifies the memory interface, eases the task of writing applications and creating partitions, and makes applications platform independent. The MMP is incorporated into an existing CCM compiler. It is shown that the MMP can increase the compiler's functionality and efficiency. / Master of Science

In the recent years threaded run-to-run (RtR) control algorithms have experienced drawbacks under certain circumstances, one such trait is when applied to high-mix of products such as in Application Specific Integrated Circuits (ASIC) foundries. The variations in the process are a function of the product being manufactured as well as the tool being used. The presence of semiconductor layers increases the number of times the lithography process must be repeated. Successive layers having different patterns must be exposed using different reticles/masks in order to maximize tool utilizations. The objectives of this research are to develop a set of methodologies for evaluation and extension of threaded control applied to overlay. This project defines methods to quantify the efficacy of threaded controls, finds the drawbacks of threaded control under production of high mix of semiconductors and suggests extensions and alternatives to improve threaded control. To evaluate the performance of threaded control, extensive simulations were performed in MATLAB. The effects of noise, disturbances, sampling and delays on the control and estimation performance of threaded controller were studied through these simulations. Based on the results obtained, several ideas to extend threaded control by reducing overall number of threads, by improving thread definitions and combination have been introduced. A unique idea of sampling the measurements dynamically based on the estimation accuracy is also presented. Future work includes implementing the extensions to threaded control suggested in this work in real production data and comparing the results without the use of those methods. Future work also includes building new alternatives to threaded control. / text

Submitted by MARIA ROSA FELIX DE SOUSA GOMIDE GUIMARÃES (DINTER) null (mariarosa@saolucas.edu.br) on 2016-11-25T14:46:15Z No. of bitstreams: 1 TESE DOUTORADO Maria Rosa Final.pdf: 1423380 bytes, checksum: 7002561449c42c6a10d037b7ac5e7381 (MD5) / Approved for entry into archive by Felipe Augusto Arakaki (arakaki@reitoria.unesp.br) on 2016-11-29T13:58:37Z (GMT) No. of bitstreams: 1 guimaraes_mrfsg_dr_araca.pdf: 1423380 bytes, checksum: 7002561449c42c6a10d037b7ac5e7381 (MD5) / Made available in DSpace on 2016-11-29T13:58:37Z (GMT). No. of bitstreams: 1 guimaraes_mrfsg_dr_araca.pdf: 1423380 bytes, checksum: 7002561449c42c6a10d037b7ac5e7381 (MD5) Previous issue date: 2016-11-22 / Objetivos: Analisar histologicamente e histometricamente o efeito do RTR® em defeitos ósseos cirúrgicos críticos em tíbias de ratos no processo de reparo ósseo. Materiais e Métodos: Defeitos ósseos críticos foram criados nas tíbias de 32 ratos Wistar divididos em dois grupos: Grupo Coágulo e Grupo RTR®. Após o período experimental de 30 e 90 dias, os animais foram sacrificados e as peças incluídas em parafina, cortadas e coradas com hematoxilina e eosina. Dois parâmetros foram analisados: a área óssea total neoformada (AON) e a área óssea da cortical neoformada (ACN). A análise estatística foi realizada nos dois períodos de observação pela análise de variância (ANOVA) e pelo Teste de Tukey. Resultados: Todos os grupos demonstraram reparo ósseo superior quando comparados ao Grupo Coágulo 30 dias nos dois parâmetros analisados. O Grupo RTR®, em 30 e 90 dias, apresentou reparo da cortical óssea e formações de tecido ósseo na região central do defeito maior do que no Grupo Coágulo de 90 dias, que apresentou reparo parcial da cortical óssea e poucas formações de tecido ósseo na região do defeito (p<0,05). Conclusões: O RTR® favoreceu a neoformação óssea no modelo experimental adotado podendo ser indicado em casos de cavidades ósseas de tamanho crítico. / Objectives: To analyze histologically and histometrically the effect of RTR® on critical surgical bone defects in rat tibiae in the bone repair process. Materials and Methods: Critical bone defects were created in the tibia of 32 Wistar rats divided into two groups: Clot Group and RTR® Group. After the experimental period of 30 and 90 days, the animals were sacrificed and the paraffin embedded pieces were cut and stained with hematoxylin and eosin. Two parameters were analyzed: total neoformed bone area (AON) and bone area of neoformed cortical (ACN). Statistical analysis was performed in the two observation periods by analysis of variance (ANOVA) and Tukey's test. Results: All groups demonstrated superior bone repair when compared to the Clot Group 30 days in the two analyzed parameters. The RTR® Group, in 30 and 90 days, presented repair of the cortical bone and bone tissue formations in the central region of the defect greater than in the 90-day Clot Group, which presented partial repair of the cortical bone and few bone tissue formations in the region of the defect (p <0.05). Conclusions: The RTR® favored the bone neoformation in the adopted experimental model and can be indicated in cases of bone of critical size.

Tato práce se zabývá technologiemi velkých dat v kontextu měření parametrů sítě. Popisuje téma velkých dat a jejich využití, představuje základní parametry sítě, jejich měření a metody zhodnocení. Vyhodnocuje RTR NetTest aplikaci, testovací proceduru a měřené parametry. Byla vytvořena skupina nástrojů pro posouzení základních kvantitativních parametrů mobilní sítě na základě dat z databáze RTR. Rozbor denního efektu shrnuje časovou proměnlivost sítě. Chování v prostoru je posouzeno binováním a shlukovou analýzou, současně se srovnáním řízeného testování a crowdsourcingu.

FPGAs (Field Programmable Gate Arrays) dinamicamente reconfiguráveis (DR-FPGAs) são soluções promissoras para muitos sistemas embarcados devido a potencial redução de área de silício. Metodologias de projeto e ferramentas CAD relacionadas são ainda muito limitadas para auxiliarem os projetistas a encontrarem soluções dinamicamente reconfiguráveis para diferentes aplicações. Este trabalho propõe uma metodologia de projeto que combina modelos de alto nível em SystemC, técnicas de projeto de baixo nível e a metodologia de projeto modular da XILINX. SystemC foi utilizada para representar o comportamento de alto nível não temporizado e não-RTL, bem como o baixo nível RTL-DCS (Chaveamento Dinâmico de Circuitos). Um estudo de caso da Banda Base de um Controlador Bluetooth foi desenvolvido. Duas partições temporais foram testadas em nove diferentes DR-FPGAs. A exploração espacial mostrou que 33% das soluções investigadas atenderam a restrição da especificação de 625µs de tempo do quadro do pacote Bluetooth, deixando diferentes parcelas de recursos livres que podem ser explorados para acomodar outros módulos IP de sistemas mais complexos no mesmo dispositivo. / Dynamically Reconfigurable Field Programmable Gate Arrays (DR-FPGAs) are promising solutions for many embedded systems due to the potential silicon area reduction. Design methodologies and related CAD tools are still very limited to assist designers to encounter dynamically reconfigurable solutions for different applications. This work proposes a design methodology that combines high level SystemC models and design techniques with the low level modular design proposed by Xilinx. SystemC has been used to represent the high level untimed non-RTL behavior as well as the low level RTL-DCS (Dynamic Circuit Switching). A Bluetooth Baseband unit case study was performed. Two temporal-functional partitions were evaluated on nine different target DR-FPGAs. The design space exploration showed that 33% of the investigated solutions complied with the 625µs Bluetooth packet time frame specification leaving different amounts if free resources that may be explored to accommodate other IP modules of more complex systems on the same device.

FPGAs (Field Programmable Gate Arrays) dinamicamente reconfiguráveis (DR-FPGAs) são soluções promissoras para muitos sistemas embarcados devido a potencial redução de área de silício. Metodologias de projeto e ferramentas CAD relacionadas são ainda muito limitadas para auxiliarem os projetistas a encontrarem soluções dinamicamente reconfiguráveis para diferentes aplicações. Este trabalho propõe uma metodologia de projeto que combina modelos de alto nível em SystemC, técnicas de projeto de baixo nível e a metodologia de projeto modular da XILINX. SystemC foi utilizada para representar o comportamento de alto nível não temporizado e não-RTL, bem como o baixo nível RTL-DCS (Chaveamento Dinâmico de Circuitos). Um estudo de caso da Banda Base de um Controlador Bluetooth foi desenvolvido. Duas partições temporais foram testadas em nove diferentes DR-FPGAs. A exploração espacial mostrou que 33% das soluções investigadas atenderam a restrição da especificação de 625µs de tempo do quadro do pacote Bluetooth, deixando diferentes parcelas de recursos livres que podem ser explorados para acomodar outros módulos IP de sistemas mais complexos no mesmo dispositivo. / Dynamically Reconfigurable Field Programmable Gate Arrays (DR-FPGAs) are promising solutions for many embedded systems due to the potential silicon area reduction. Design methodologies and related CAD tools are still very limited to assist designers to encounter dynamically reconfigurable solutions for different applications. This work proposes a design methodology that combines high level SystemC models and design techniques with the low level modular design proposed by Xilinx. SystemC has been used to represent the high level untimed non-RTL behavior as well as the low level RTL-DCS (Dynamic Circuit Switching). A Bluetooth Baseband unit case study was performed. Two temporal-functional partitions were evaluated on nine different target DR-FPGAs. The design space exploration showed that 33% of the investigated solutions complied with the 625µs Bluetooth packet time frame specification leaving different amounts if free resources that may be explored to accommodate other IP modules of more complex systems on the same device.