Global ETD Search

1	A Multiplexed Memory Port for Run Time Reconfigurable Applications Atwell, James W. 21 December 1999 (has links) Configurable computing machines (CCMs) are available as plug in cards for standard workstations. CCMs make it possible to achieve computing feats on workstations that were previously only possible with super computers. However, it is difficult to create applications for CCMs. The development environment is fragmented and complex. Compilers for CCMS are emerging but they are in their infancy and are inefficient. The difficulties of implementing run time reconfiguration (RTR) on CCMs are addressed in this thesis. Tools and techniques are introduced to simplify the development and synthesis of applications and partitions for RTR applications. A multiplexed memory port (MMP) is presented in JHDL and VHDL that simplifies the memory interface, eases the task of writing applications and creating partitions, and makes applications platform independent. The MMP is incorporated into an existing CCM compiler. It is shown that the MMP can increase the compiler's functionality and efficiency. / Master of Science Field programmable gate arrays JHDL Memory reconfigurable VHDL RTR
2	SYNTHESIS OF VIRTUAL PIPELINES ON VIRTEX-BASED FPGAs DASASATHYAN, SRINIVASAN 11 October 2001 (has links) No description available. partial reconfiguration virtex based board virtual pipeline JHDL SBLOX (serial blocks)
3	JHDLBits: An Open-Source Model for FPGA Design Automation Poetter, Alexandra Vanessa 22 September 2004 (has links) Today's Field Programmable Gate Array (FPGA) research community could use an extensible tool flow enabling designers to examine new algorithms and new methods of interacting with FPGA configurations. One such flow is JHDLBits, which integrates two prominent FPGA design environments: JHDL and JBits. JHDLBits offers the low-level access and control provided by JBits with the high-level structural circuit design of JHDL. Furthermore, the JHDLBits flow provides greater control of resource manipulation, placement, and routing, and gives researchers a sandbox to explore advanced interactions with FPGA configurations. This thesis presents the overall architecture of the open-source JHDLBits project. Details are provided on how the core components -- JHDL, JBits3 for Virtex-II, the ADB connectivity database, and VTsim, a Virtex-II device simulator -- are linked together to provide an integrated design environment. Strategies and philosophies of the open source movement are also examined to successfully establish the support for and involvement of the FPGA research community throughout the JHDLBits open source endeavor. / Master of Science Hardware Description Language JHDLBits JHDL JBits Field programmable gate arrays Design Automation
4	A Device-Level FPGA Simulator Hunter, Jesse Everett III 03 August 2004 (has links) In the realm of FPGAs, many tool vendors offer behaviorally-based simulators aimed at easing the complexity of large FPGA designs. At times, a behaviorally-modeled design does not work in hardware as expected or intended. VTsim, a Virtex-II device simulator, was designed to resolve this and many other design problems by providing a window into the FPGA fabric via a virtual device. VTsim is an event-driven device simulator modeled at the CLB level with multiple clock domain support. Utilizing JBits3 and ADB, VTsim enables simulation and examination of all resources within an FPGA via a virtual device. The only input required by VTsim is a bitstream, which can be generated from any tool suite. The simulator is part of the JHDLBits open-source project, and was designed for rapid response, low memory usage, and ease of interaction. / Master of Science Field programmable gate arrays Device Simulator JHDLBits JHDL JBits VTsim Virtex-II Xilinx
5	Designing, Debugging, and Deploying Configurable Computing Machine-based Applications Using Reconfigurable Computing Application Frameworks Slade, Anthony Lynn 07 March 2003 (has links) (PDF) Configurable computing machines (CCMs) offer high-performance application acceleration with custom hardware. They are also dynamically reconfigurable and give significant internal visibility. Such features are useful throughout the design, debug, and deploy stages of CCM-based application development. However traditional, monolithic design tools do not offer adequate support for all of these development stages. This thesis describes a specification for a reconfigurable computing application framework (RCAF) which is more suitable for CCM application development. It also describes an implementation of such an RCAF. This RCAF improves the efficiency of application design and debugging. It also establishes an application architecture framework which helps to build up not only the hardware design, but also the application software and user interface. Applications built using this small, deployable RCAF may also perform significantly better due to the dynamic hardware reconfiguration features included with the RCAF. CCM FPGA RCAF deploy framework reconfigurable configurable computing machine computing application design debug circuit visualization JHDL Electrical and Computer Engineering

1

Page generated in 0.0308 seconds