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Along with emergence of embedded systems, operating systems are now widely used in various applications on environments other than the desktops and workstations, such as house electrical appliances and mobile devices. Diverse applications have different requirement on the software architectures of operating systems, They can be satisfied by adopting configurable operating systems. In this research, utilizing modulization and inter-module communication channel, we developed a software architecture configurable operating system. By configuring inside channels with interfacing and protection components, we can realize an operating system into various software architectures.

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Reconfigurable computing architectures are gaining popularity as a replacement for general-purpose architectures for many high performance embedded applications. These machines support parallel computation and direct the data from the producers of an intermediate result to the consumers over custom pathways. The Wormhole Run-time Reconfigurable (RTR) computing architecture is a concept developed at Virginia Tech to address the weaknesses of contemporary FPGAs for configurable computing. The Stallion chip is a full-custom configurable computing "FPGA"-like integrated circuit with a coarse grained nature. Based on the result of the first generation device, the Colt chip, the Stallion chip is a follow-up configurable computing chip. This thesis focuses on the VLSI layout implementation of the Stallion chip. Effort has been made to explain many facts and advantages of the Wormhole Configurable Computing Machine (CCM). Design techniques, strategies, circuit characterization, performance estimation, and ways to solve problems when using CAD layout design tools are illustrated. / Master of Science

Microprocessors have difficulties addressing the demands of today's high-performance embedded applications. ASICs are a good solution to the speed concerns, but their cost and time to market can make them impractical for some needs. Configurable Computing Machines (CCMs) provide a cost-effective way of creating custom components; however, oftentimes it would be better if there were a way to change the configuration of the CCM as a program is executing. An efficient way of doing this is with Runtime Reconfigurable (RTR) computing architectures. In an RTR system, one challenging problem is the assignment of operators onto the array of processing elements (PEs) in a way as to simultaneously minimize both the number of PEs used and the number of interconnections between them for each configuration. This job is automated through the use of a software program referred to as the Spatial Partitioner. The design and implementation of the Spatial Partitioner is the subject of this work. The Spatial Partitioner developed herein uses an iterative, recursive algorithm along with cluster refinement to find a reasonably efficient allocation of operators onto the target platform in a reasonable amount of time. Information about the topology of the target platform is used throughout the execution of the algorithm to ensure that the resulting solution is legal in terms of layout. / Master of Science

Les systèmes électroniques embarqués à bord des aéronefs rassemblent des informations sur l’environnement qui les entourent au moyen de différents types de capteurs. À l’heure actuelle, l’acquisition des signaux générés par ces capteurs se fait au moyen de circuits électroniques d’interfaçage dédiés à un type de capteur en particulier, ce qui limite les possibilités d’évolution des calculateurs de bord.Nos travaux visent à remplacer ces circuits d’interfaçage par une interface dite versatile, capable de faire l’acquisition de signaux issus de différents types de capteurs. L’environnement dans lequel les systèmes avioniques sont amenés à fonctionner est particulièrement difficile, notamment par la présence de modes communs parasites importants, supérieures à plusieurs dizaines de volts. Après une exploration détaillée de cet environnement, nous proposons une architecture d’interface versatile, basée sur un ASIC mixte et un FPGA. L’ASIC est chargé du conditionnement analogique des signaux et de leur conversion dans le domaine numérique, et peut-être configuré à plusieurs niveaux (gains, offsets, impédances...). Le FPGA comprend les différents traitements numériques nécessaires à l’extraction de l’information contenue dans les signaux. Nous proposons de plus une méthode mixte permettant de corriger les imprécisions analogiques, telles que les défauts d’appairage, souvent critiques dans l’acquisition de signaux différentiels. Un circuit de test a été réalisé dans une technologie CMOS High Voltage 0.35µm afin de valider les différents principes proposés dans nos travaux. / Avionic embedded systems sense their environment through the use of various sensors. Currently, the electrical signals generated by these sensors are acquired by dedicated interface circuits, which limits the functionalities that can be implemented in the computer and slows down their evolution.Our work aims at replacing these interfacing circuits by a more flexible interface, called versatile interface, which has the ability to acquire different kind of signals. Avionic embedded systems usually operate in a pretty harsh environment, in which important common mode voltages of more than thirty volts can superimpose to useful signals. After a thorough exploration of this environment and its specifities, we propose an architecture of the versatile interface, based on a mixed signal ASIC and a FPGA. The ASIC includes a programmable analog signal conditioning stage which is able to withstand the high voltages present in the harsh avionic environment. The FPGA processes the different signals and extract the useful information from them. We also propose method which allows to correct the analog imprecisions due to mismatch or temperature drifts. This method uses analog and digital processing, and allow our versatile interface to be immune to process or temperature variations. A test circuit has been realized in a high voltage 0.35µm CMOS technology, in order to validate the different principles that we propose in this work.

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International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California / Based on a fourty year experience in Telemetry, acquired on the European Space Program, IN-SNEC company (Zodiac group) has designed a versatile, modular and customable telemetry system for Airbus A380 aircraft program. This Aircraft Telemetry System (TMA-2000) comes with a large set of acquisition boards allowing numerous digital and analog inputs. The major innovation of this system lies in its modularity which allows the user to configure his acquisition chain in function of his monitoring needs and the use of an Ethernet link for its configuration as well as for telemetry output data flow.

This dissertation presents a synthesis of methods for structural optimization of aircraft wing boxes. The optimization problem considered herein is the minimization of structural weight with respect to component sizes, subject to stress constraints. Different aspects of structural optimization methods representing the current state-of-the-art are discussed, including sequential quadratic programming, sensitivity analysis, parameterization of design variables, constraint handling, and multiple load treatment. Shortcomings of the current techniques are identified and a B-spline parameterization representing the structural sizes is proposed to address them. A new configurable B-spline parameterization method for structural optimization of wing boxes is developed that makes it possible to flexibly explore design spaces. An automatic scheme using different levels of B-spline parameterization configurations is also proposed, along with a constraint aggregation method in order to reduce the computational effort. Numerical results are compared to evaluate the effectiveness of the B-spline approach and the constraint aggregation method. To evaluate the new formulations and explore design spaces, the wing box of an airliner is optimized for the minimum weight subject to stress constraints under multiple load conditions. The new approaches are shown to significantly reduce the computational time required to perform structural optimization and to yield designs that are more realistic than existing methods.