Thèse numérisée par la Division de la gestion de documents et des archives de l'Université de Montréal.

Thèse numérisée par la Division de la gestion de documents et des archives de l'Université de Montréal

With the introduction of partially reconfigurable FPGAs, we are now able to perform dynamic changes to hardware running on an FPGA without halting the operation of the design. Module based partial reconfiguration allows the hardware designer to create multiple hardware modules that perform different tasks and swap them in and out of designated dynamic regions on an FPGA. However, the current mainstream partial reconfiguration flow provides a limited and inefficient approach that requires a strict set of guidelines to be met. This thesis introduces BitMaT, a tool that provides the low-level bitstream manipulation as a member tool of an alternative, automated, modular partial reconfiguration flow. / Master of Science

This master's thesis dissertates of partial reconfiguration methods based on programmable structures. In theoretical part it deals with difference and modular-based method of Xilinx's FPGAs Partial reconfiguration. Options of both reconfiguration techniques were written for Spartan 3, Virtex II, Virtex 4 and Virtex 5 processors. Diference-based method was in practical part tested on Spartan 3E Starter Kit and modular-based on ML501 board. All configuration bitstreams are included on CD. Xilinx Inc. provided all needed software tools such as ISE9.2i and PlanAHEAD.

<p>Today, wireless communications is used more then ever before. Wired systems are replaced with wireless versions. New methods and transmission standards are developed and tested. The purpose of this thesis is development of a flexible high-performance System Test Platformfor test of the SoCTRix Wireless LAN Transceiver. </p><p>The result is a Xilinx Virtex-II FPGA based System Test Platform board with CardBus PC Card interface to a computer. The hardware achieved has the following features:</p><p>- 8-layer PCB</p><p>- PCMCIA CardBus PC Card interface, enabling 133 MB/s data throughput</p><p>- 1M Gate Virtex-II FPGA with reprogrammable configuration memory</p><p>- Debugging via LEDs and Logic Analyzer connectors</p><p>- 2x SPI EEPROM</p><p>- 40 MHz system clock</p><p>- Easy connection of two daughter-boards</p><p>Specially designed for wireless transmitter development, can also be used for other computer related highperformance applications.</p>

<p>Test Tools are very important in the design of a system. They generally simulate a working environment, only at a higher</p><p>speed, or with less frequently occurring test cases. In the verification of protocols based on the Fibre Channel physical layer,</p><p>this becomes a necessity, as errors can be non-existent or very unusual in normal operating environments. Most systems need</p><p>to be able to handle these unexpected events nonetheless. Therefore, there is a need for a method of introducing these errors</p><p>in a controlled way.</p><p>A bit error generation and logging tool for two proprietary protocols based on the Fibre Channel physical layer has been</p><p>developed. The hardware platform consists mainly of a Virtex II Pro FPGA with accompanying I/O support. Control of the</p><p>hardware is handled by a graphical user interface residing on a PC. Communication between the hardware and the PC is</p><p>handled with a UART. The final implementation can handle four parallel one way links, or two full duplex links,</p><p>independently. This report describes the implementation and the necessary theoretical background for this.</p>

Today, wireless communications is used more then ever before. Wired systems are replaced with wireless versions. New methods and transmission standards are developed and tested. The purpose of this thesis is development of a flexible high-performance System Test Platformfor test of the SoCTRix Wireless LAN Transceiver. The result is a Xilinx Virtex-II FPGA based System Test Platform board with CardBus PC Card interface to a computer. The hardware achieved has the following features: - 8-layer PCB - PCMCIA CardBus PC Card interface, enabling 133 MB/s data throughput - 1M Gate Virtex-II FPGA with reprogrammable configuration memory - Debugging via LEDs and Logic Analyzer connectors - 2x SPI EEPROM - 40 MHz system clock - Easy connection of two daughter-boards Specially designed for wireless transmitter development, can also be used for other computer related highperformance applications.

Test Tools are very important in the design of a system. They generally simulate a working environment, only at a higher speed, or with less frequently occurring test cases. In the verification of protocols based on the Fibre Channel physical layer, this becomes a necessity, as errors can be non-existent or very unusual in normal operating environments. Most systems need to be able to handle these unexpected events nonetheless. Therefore, there is a need for a method of introducing these errors in a controlled way. A bit error generation and logging tool for two proprietary protocols based on the Fibre Channel physical layer has been developed. The hardware platform consists mainly of a Virtex II Pro FPGA with accompanying I/O support. Control of the hardware is handled by a graphical user interface residing on a PC. Communication between the hardware and the PC is handled with a UART. The final implementation can handle four parallel one way links, or two full duplex links, independently. This report describes the implementation and the necessary theoretical background for this.

Field-programmable gate arrays (FPGAs) are excellent devices for high-performance computing, system-on-chip realization, and rapid system prototyping. While FPGAs offer flexibility and performance, they continue to lag behind application specific integrated circuit (ASIC) performance and power consumption. As manufacturing technology improves and IC feature size decreases, FPGAs may further lag behind ASICs due to interconnection scalability issues. To improve FPGA scalability, this thesis proposes an architectural enhancement to improve global communications in large FPGAs, where chip-length programmable interconnects are slow. It is expected that this architectural enhancement, based on wire emulation techniques, can reduce chip-length communication latency and routing congestion. A prototype wire emulation system that uses FPGA self-reconfiguration as a non-traditional means of intra-FPGA communication is implemented and verified on a Xilinx Virtex-II XC2V1000 FPGA. Wire emulation benefits and impact to FPGA architecture are examined with quantitative and qualitative analysis. / Master of Science

In the realm of FPGAs, many tool vendors offer behaviorally-based simulators aimed at easing the complexity of large FPGA designs. At times, a behaviorally-modeled design does not work in hardware as expected or intended. VTsim, a Virtex-II device simulator, was designed to resolve this and many other design problems by providing a window into the FPGA fabric via a virtual device. VTsim is an event-driven device simulator modeled at the CLB level with multiple clock domain support. Utilizing JBits3 and ADB, VTsim enables simulation and examination of all resources within an FPGA via a virtual device. The only input required by VTsim is a bitstream, which can be generated from any tool suite. The simulator is part of the JHDLBits open-source project, and was designed for rapid response, low memory usage, and ease of interaction. / Master of Science