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This dissertation constitutes two major sections. In the first major section, a kinetic analysis was established to investigate the electromigration (EM), enhanced intermetallic compound (IMC) growth and void formation for Sn-based Pb-free solder joints to Cu under bump metallization (UBM). The model takes into account the interfacial intermetallic reaction, Cu-Sn interdiffusion, and current stressing. A new approach was developed to derive atomic diffusivities and effective charge numbers based on Simulated Annealing (SA) in conjunction with the kinetic model. The finite difference (FD) kinetic model based on this approach accurately predicted the intermetallic compound growth when compared to empirical observation. The ultimate electromigration failure of the solder joints was caused by extensive void formation at the intermetallic interface. The void formation mechanism was analyzed by modeling the vacancy transport under electromigration. The effects of current density and Cu diffusivity in Sn solder were also investigated with the kinetic model. The second major section describes the integration of Step and Flash Imprint Lithography (S-FIL®) into an industry standard Cu/low-k dual damascene process. The yield on a Back End Of the Line (BEOL) test vehicle that contains standard test structures such as via chains with 120 nm vias was established by electrical tests. S-FIL shows promise as a cost effective solution to patterning sub 45 nm features and is capable of simultaneously patterning two levels of interconnect structures, which provides a low cost BEOL process. The critical processing step in the integration is the reactive ion etching (RIE) process that transfers the multilevel patterns to the inter-level dielectrics (ILD). An in-situ, multistep etch process was developed that gives excellent pattern structures in two industry standard Chemical Vapor Deposited (CVD) low-k dielectrics. The etch process showed excellent pattern fidelity and a wide process window. Electrical testing was conducted on the test vehicle to show that this process renders high yield and consistent via resistance. Discussions of the failure behaviors that are characteristic to the use of S-FIL are provided. / text

Materials, Processes, and Characterization of Extended Air-gaps for the Intra-level Interconnection of Integrated Circuits Seongho Park 157 pages Directed by Dr. Paul A. Kohl and Dr. Sue Ann Bidstrup Allen The integration of an air-gap as an ultra low dielectric constant material in an intra-metal dielectric region of interconnect structure in integrated circuits was investigated in terms of material properties of a thermally decomposable sacrificial polymer, fabrication processes and electrical performance. Extension of the air-gap into the inter-layer dielectric region reduces the interconnect capacitance. In order to enhance the hardness of a polymer for the better process reliabilities, a conventional norbornene-based sacrificial polymer was electron-beam irradiated. Although the hardness of the polymer increased, the thermal properties degraded. A new high modulus tetracyclododecene-based sacrificial polymer was characterized and compared to the norbornene-based polymer in terms of hardness, process reliability and thermal properties. The tetracyclododecene-based polymer was harder and showed better process reliability than the norbornene-based sacrificial polymer. Using the tetracyclododecene-based sacrificial polymer, a single layer Cu/air-gap and extended Cu/air-gap structures were fabricated. The effective dielectric constant of the air-gap and extended air-gap structures were 2.42 and 2.17, respectively. This meets the requirements for the 32 nm node. Moisture uptake of the extended Cu/air-gap structure increased the effective dielectric constant. The exposure of the structure to hexamethyldisilazane vapor removed the absorbed moisture and changed the structure hydrophobic, improving the integration reliability. The integration processes of the air-gap and the extended air-gap into a dual damascene Cu metallization process has been proposed compared to state-of-the-art integration approaches.