This project focused on creating a PCB prototype to work with KTH's newly purchased FPGAs. This PCB is meant to be used to expand the FPGA's IO, as it did not have enough LEDs or switches to be used in some courses at the Embedded Systems program at KTH. An original design for the PCBs existed before this thesis was started, but it needed to be developed to meet the new requirements. Several prototypes were developed by first designing the PCB in KiCad. The design in KiCad then formed the basis for the physical prototype, which was milled out before the components could be soldered. The final functional prototype was approximately the size of the FPGA board and was connected to it by the FPGA's GPIO extension pins. The result of this thesis was a prototype that fulfilled the requirements and was ready for production. / Detta projekt fokuserade utifrån att skapa en PCB prototyp för att fungera med KTH:s nya inköpta FPGAs. PCBn som skulle skapas är ämnad att användas till att utöka en FPGAs IO, eftersom den inte hade tillräckligt med LEDar och switchar för att kunna användas i vissa kurser i programmet inbyggda system på KTH. Det fanns en ursprunglig design för påbyggnadskortet innan detta projekt började, men den behövde utvecklas för att uppfylla de nya krav som ställdes. Flera prototypkonstruktioner togs fram genom att först designa PCBn i KiCad. Designen i KiCad låg sedan som grund för den fysiska prototypen vilken frästes ut innan komponenterna kunde lödas fast. Den slutgiltiga funktionella prototypen var ungefär samma storlek som FPGA-brädan och anslöts till den existerande brädans GPIO-pins. Resultatet var en prototyp som uppfyllde de krav som ställts och som var redo för produktion på en större skala.

The Large Hadron Collider at CERN is scheduled to undergo upgrades in 2026-2028 to significantly increase its luminosity. These upgrades, while providing the experiments with a higher collision rate, pose a number of challenges to the design of the hardware and software in the detectors. The Tile Calorimeter (a scintillating sampling calorimeter read out by photomultiplier tubes) at the ATLAS experiment will have its read-out electronics completely replaced to enable performance and reliability improvements.  Advances in electronics, new requirements due to the luminosity upgrade as well as lessons learned from the current readout scheme drove development with the goals to partition the readout into small independent units with full granularity readout and a robust mitigation strategy for radiation induced errors. To verify the functionality of the new system while retaining backward compatibility a "Demonstrator'' has been developed to emulate the current functionality while using new and improved hardware. The board responsible for managing digitized calorimeter data and communicating with the off-detector electronics, called the DaughterBoard, is the main focus of this thesis. It has two electrically isolated sides for redundancy where each side consists of voltage regulators, two optical transceivers, a GigaBit transceiver chip (for clocking and configuration) and a Kintex FPGA for data processing. In addition to data management and transmission, the FPGA (and every other component) needs to be able to withstand the effects of radiation both in terms of total dose (ionization and displacement damage) and due to single event effects. The DaughterBoard was developed with this in mind and has undergone several radiation tests during its development to verify reliability and fault tolerance. / CERN