As the speed and power demands on Buck converters continue to increase, it has become time to replace the linearly-controlled conventional Buck converter. Digital circuits, such as microprocessors, are requiring higher dynamic currents, at lower voltages, than ever before. Traditionally, such Buck converters have been controlled by linear voltage-mode or current-mode control methods. While these controllers offer such advantages as fixed switching frequencies and zero steady-state error, their reaction speed is inherently limited by their bandwidth which is a fraction of the converter switching frequency. Therefore, to improve the transient response of a Buck converter in a practical manner, four novel ideas are presented in this thesis. The first contribution is an analog “charge balance controller”. The control method utilizes the concept of capacitor charge balance to achieve a near-optimal transient response for Buck converters undergoing a rapid load change. Unlike previous work, the proposed controller does not require expensive and/or slow analog multipliers/dividers. In addition, the nominal inductance value is not required by the proposed controller. Simulation and experimental results demonstrate a significant improvement in transient performance over that of a linear voltage-mode controller. For low duty cycle applications, the unloading transient performance of a Buck converter tends to be poor when compared to the corresponding loading transient performance. Therefore, the second contribution is an auxiliary circuit and an analog auxiliary controller which drastically improves the performance of a Buck converter undergoing an unloading transient. Significant overshoot reduction was observed over that of a linearly-controlled conventional Buck converter. The third contribution is a digital implementation of the aforementioned “charge balance control” concept. Through digital implementation the control law is extended to include load-line regulation. Unlike previous work, large lookup tables are not required to perform complex mathematical functions, thus the number of required gates is significantly reduced. The final contribution is a digital implementation of the “charge balance controller” capable of operating with the previously-mentioned auxiliary circuit. This complete solution is capable of improving the voltage deviation caused by loading and unloading transients. In addition, the combined auxiliary circuit and control law is extended to load-line regulation applications. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2010-01-31 23:01:24.606

Improved transient performance and converter miniaturization are the major driving factors behind high frequency operation of switching power supplies. However, high speed operation is limited by topology, control, semiconductor, and packaging technologies. The inherent mitigation of switching loss in resonant converters makes them prime candidates for use when the limits of switching frequency are pushed. The goal of this thesis is to address two areas that practically limit the achievable switching frequency of resonant topologies. Traditional control methods based on single cycle response are impractical at high frequency; forcing the use of pulse density modulation (PDM) techniques. However, existing pulse density modulation strategies for resonant converters in dc/dc applications suffer from: • High semiconductor current stress. • Slow response and large filter size determined by the low modulating frequency. • Possibly operating at fractions of resonant cycles leading to switching loss; thereby limiting the modulating frequency. A series resonant converter with variable frequency PDM (VF-PDM) with integral resonant cycle control is presented to overcome the limitations of existing PDM techniques to enable efficient operation with high switching frequency and modulating frequency. The operation of the circuit is presented and analyzed, with a design procedure given to achieve fast transient performance, small filter size, and high efficiency across the load range with current stress comparable to conventional control techniques. It is shown that digital implementation of the controller can achieve favourable results with a clock frequency four times greater than the switching frequency. Driving the synchronous rectifiers is a considerable challenge in high current applications operating at high switching frequency. Resonant gate drivers with continuous inductor current experience excessive conduction loss, while discontinuous current drivers are subject to slow transitions and high peak current. Current source drivers suffer from high component count and increased conduction loss when applied to complementary switches. A dual-channel current source driver is presented as a means of driving two complementary switches. A single coupled inductor with discontinuous current facilitates low conduction loss by transferring charge between the MOSFET gates to reduce the number of semiconductors in the current path, and reducing the number of conduction intervals. The operation of the circuit is analyzed, and a design procedure based on minimization of the total synchronous rectifier loss is presented. Implementation of the digital logic to control the driver is discussed. Experimental results at megahertz operating frequencies are presented for both areas addressed to verify the theoretical results. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2012-09-09 20:43:56.997

The proposed research objective is to develop, test, and evaluate a mixer and charger-supply CMOS IC that derives and mixes energy and power from mixed sources to accurately supply a miniaturized system. Since the energy-dense source stores more energy than the power-dense source while the latter supplies more power than the former, the proposed research aims to develop an IC that automatically selects how much and from which source to draw power to maximize lifetime per unit volume. Today, the state of the art lacks the intelligence and capability to select the most appropriate source from which to extract power to supply the time-varying needs of a small system. As such, the underlying objective and benefit of this research is to reduce the size of a complete electronic system so that wireless sensors and biomedical implants, for example, as a whole, perform well, operate for extended periods, and integrate into tiny spaces.

Switching device power losses place critical limits on the design and performance of high-frequency integrated DC-DC converters. Especially, the layout of metal interconnects in lateral power MOSFETs has a profound effect on their on-resistances and conduction power losses. This thesis presents an analytical interconnect modeling and layout optimization technique for large-area power MOSFETs. The layout optimization of 24V LDMOS transistors in the area of 1 mm2 has achieved an improvement of 55 % in its on-resistance. The simulation result has been verified by experimental measurements on a test chip fabricated in TSMC 0.25 µm HV CMOS technology. In addition, this thesis presents an optimized output stage design methodology for the implementation of a 4 MHz, 12V to 1V integrated DC-DC converter. A segmented output stage scheme is employed to increase the converter efficiency at light load conditions. The peak efficiency of 84% was achieved at load current of 2 A.

Switching device power losses place critical limits on the design and performance of high-frequency integrated DC-DC converters. Especially, the layout of metal interconnects in lateral power MOSFETs has a profound effect on their on-resistances and conduction power losses. This thesis presents an analytical interconnect modeling and layout optimization technique for large-area power MOSFETs. The layout optimization of 24V LDMOS transistors in the area of 1 mm2 has achieved an improvement of 55 % in its on-resistance. The simulation result has been verified by experimental measurements on a test chip fabricated in TSMC 0.25 µm HV CMOS technology. In addition, this thesis presents an optimized output stage design methodology for the implementation of a 4 MHz, 12V to 1V integrated DC-DC converter. A segmented output stage scheme is employed to increase the converter efficiency at light load conditions. The peak efficiency of 84% was achieved at load current of 2 A.

The United Nations has declared 2012 the ``International Year of Sustainable Energy for All''. A substantial portion of the world's population (some 1.3 billion people) currently live without electricity and development efforts to reach them are progressing relatively slowly. This thesis follows the development of a technology which can enable community owned and operated microgrids to emerge based solely on the local supply and demand of that community. Although this thesis ends with the technical analysis of a DC/DC converter, there is a significant amount of background to cover in order to properly understand the context in which it will be used. After providing an introduction into typical rural electrification efforts and pointing out some of the shortcomings of these projects, this thesis introduces some cutting edge efforts which combine solar home system technology with cellular technology and discusses the benefits of such a marriage of technology. Next, the research proposes some tweaks to this novel technology and provides a high-level economic demonstration of the spread of solar home systems in a community based on these modifications. It then takes this concept even further and proposes the addition of a DC/DC converter which could turn these individual solar home systems into a proper microgrid. This thesis elaborates on the development process of simulating such a microgrid in PSCAD, including the individual components of a solar home system and the specific task of designing the converter which would form the backbone of the proposed microgrid. The final simulations and analyses demonstrate a microgrid that is both technically and economically feasible for developing world applications.

Thesis (M.S.)--Missouri University of Science and Technology, 2008. / Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed May 12, 2008) Includes bibliographical references (p. 102-107).

Konstanz, Univ., Diss., 2006. / Dokument noch nicht freigegeben.

Thesis (Ph. D.)--Missouri University of Science and Technology, 2009. / Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed May 4, 2009) Includes bibliographical references.

Thesis (M.S.)--California Polytechnic State University, 2008. / Title from PDF title page; viewed on January 8, 2009. Major professor: Taufik, Ph.D. "Presented to the faculty of the College of Engineering, California Polytechnic State University." "In partial fulfillment of the requirements for the degree [of] Master of Science in Electrical Engineering." "September 2008." Includes bibliographical references (p. 102-103). Also available on microfiche.