<p>The scope for this thesis was to design a debug interface for a DSP (digital signal processor). The DSP is a research version of a Motorola 56000 that is designed for a project on asynchronous processor and for use in education.</p><p>The DSP and debug interface are controlled via a standard PC with RS232 interface equipped with Linux operation system.</p><p>In the project 4 blocks has been designed:</p><p>The first block can set the DSP core in debug mode or run mode. The second block sends a debug instruction to the DSP core, these debug instructions were prerequisite to the project. The third block enable read and write connection to the memory buses between the DSP core and the three memory blocks. The forth block can override the control signals to the memories from the DSP core.</p><p>The project also uses an UART for interpreting and sending control signals and data between the different blocks and the computer.</p><p>A text terminal program for Linux has also been programmed for handling the PC side communication.</p><p>The hardware has been constructed and tested together with a dummy DSP core and dummy memories, but it has not been tested together with the live DSP core.</p><p>The Linux program has been tested the same way and seems to do what it's supposed to, though it leaves a lot work to be easy to handle.</p>

The scope for this thesis was to design a debug interface for a DSP (digital signal processor). The DSP is a research version of a Motorola 56000 that is designed for a project on asynchronous processor and for use in education. The DSP and debug interface are controlled via a standard PC with RS232 interface equipped with Linux operation system. In the project 4 blocks has been designed: The first block can set the DSP core in debug mode or run mode. The second block sends a debug instruction to the DSP core, these debug instructions were prerequisite to the project. The third block enable read and write connection to the memory buses between the DSP core and the three memory blocks. The forth block can override the control signals to the memories from the DSP core. The project also uses an UART for interpreting and sending control signals and data between the different blocks and the computer. A text terminal program for Linux has also been programmed for handling the PC side communication. The hardware has been constructed and tested together with a dummy DSP core and dummy memories, but it has not been tested together with the live DSP core. The Linux program has been tested the same way and seems to do what it's supposed to, though it leaves a lot work to be easy to handle.

The aim of the work is the design and implementation of two circuit boards delivering learning platforms, which will consist of two separate circuit boards with ARM MCU and a programmable FPGA gate array that will be interconnectable and appropriately complemented by peripherals. These platforms will be developed by analysing current teaching and development platform solutions and then demonstrating on practical examples. The main benefit of this work should be update and simplification of existing equipment. At the same time, there is an emphasis on greater transparency of the whole solution, so that it is not too complicated for an aspiring student to familiarise himself with modern micro-controllers and programmable gate arrays and can link the simpler units into more complex ones, where the individual boards can be used as separate working units and their interconnection will provide a computationaly stronger yet more complex device.