xii, 77 leaves : ill., appendices / Title page, contents and abstract only. The complete thesis in print form is available from the University Library. / Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical Engineering, 1973

Thesis (Ph.D.) -- University of Adelaide, Dept. of Electrical Engineering, 1973.

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No description available.

The precise measurement of a capacitance difference or ratio in a digital form is very important for capacitive sensors, for CMOS process characterization as well as for the realization of precise switched-capacitor data converters, amplifiers and other circuits utilizing ratioed capacitors. This thesis introduces design techniques for on-chip capacitor ratio testing and sensor readout that utilize sigma-delta modulation and integrate the sensor capacitors into the modulator. Several single-ended circuits are introduced, and the correlated-double-sampling (CDS) technique is used in the circuits to reduce the non-ideal effects of opamps. Several simple calibration schemes for clock-feedthrough cancellation are also introduced and discussed. A fully-differential implementation is also described and various common-mode feedback schemes are discussed and analyzed. Simulation and experimental results show that these circuits can provide extremely accurate results even in the presence of non-ideal circuit effects such as finite opamp gain, opamp input offset and noise, and clock-feedthrough effect from the switches. To verify the effectiveness of the circuits and simulations, two prototype chips containing a single-ended realization and a fully-differential one were designed and fabricated in a 1.2 ��m CMOS technology. Two off-chip mica capacitors were used in the test circuits, and the measured results show that very accurate results can be obtained using these circuit techniques even with off-chip noise coupling and large parasitic capacitances. / Graduation date: 1999

Delta-sigma data converters have gained popularity in both analog-to-digital and digital-to-analog converters (ADCs and DACs) due to their simplicity, high linearity and immunity to many analog circuit imperfections. These data converters include features such as oversampling, noise-shaping, and (historically) single-bit quantization. Single-bit converters are preferred for their inherent linearity. This is a feature which multibit converters cannot realize due to the unavoidable phenomenon of element mismatch. Because of this problem, multibit converters have been largely unexplored, and the market has seen few multibit commercial products. Earlier work has shown that multibit DACs constructed with unit elements can be applied in an architecture which shapes the spectrum of the noise caused by element mismatch. The basis of this thesis is the experimental verification of such a DAC. A Xilinx 4005 FPGA is utilized to implement a 3rd-order 4-bit delta-sigma modulator and the mismatch-shaping logic, while a custom IC consisting of 16 individually-controlled differential current sources implements the unit-element DAC. The final DAC achives a Spurious Free Dynamic Range (SFDR) of 96 dB at a sampling rate of 62.5 kHz. / Graduation date: 1997

This thesis focuses on the design and analysis of an optimal filter that is capable of making one-step-ahead prediction of a bandlimited signal while attenuating unwanted noise. First, the filter optimization based on the least mean-square-error criterion is presented. Then, an exact expression for the achievable minimum mean square error (MMSE) is derived with the aid of the Toeplitz form method and Szego theory. Based on this MMSE expression, the formulae for estimating the optimal filter¡¦s in-band prediction error and out-of-band noise attenuation are derived. Finally, the optimal filter is applied to sigma-delta modulation. It shows that the modulation performance and stability are intimately related to the filter performance and can be accurately estimated by the derived formulae.

International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California / IRIG-106 Chapter 5 describes a method for encoding voice using a simple circuit to reduce the overall bit rate and still achieve good quality voice. This well described Continuously Variable Slope Delta Modulation (CVSD) circuit can be obtained using analog parts. A more stable implementation of CVSD can be obtained by designing an anti-aliasing input filter, an A/D converter, and logic. This paper describes one implementation of the CVSD using a standard A/D converter and logic.

International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada / This paper describes the design and characteristics of a digital voice encoding circuit that uses the continuously variable slope delta (CVSD) modulation/demodulation method. With digital voice encoding, the audio signal can be placed into the pulse code modulation (PCM) data stream. Some methods of digitizing voice can require a large amount of bandwidth. Using the CVSD method, an acceptable quality of audio signal is obtained with a minimum of bandwidth. Presently, there is a CVSD microchip commercially available; however, this paper will describe the design of a circuit based on individual components that apply the CVSD method. With the advances in data acquisition technology, increased bit rates, and introduction of a corresponding MIL-STD, CVSD modulated voice will become more utilized in the flight test programs and a good knowledge of CVSD will become increasingly important. This paper will present CVSD theory, supported by graphical investigations of a working circuit under different conditions. Finally, several subjects for further study into CVSD will be addressed.

This thesis describes compensation techniques for cascaded delta-sigma A/D converters (ADCs) and high-performance switched-capacitor (SC) circuits. Various correlated-double-sampling (CDS) techniques are presented to reduce the effects of the nonidealities, such as clock feedthrough, charge injection, opamp input-referred noise and offset, and finite opamp gain, in SC circuits. A CDS technique for the compensation of opamp input-referred offset and clock-feedthrough effect is examined and improved to achieve continuous operation. Experimental results show that after the compensation, the SC integrator's output signal swing is greatly increased. The effects of the analog circuitry nonidealities in delta-sigma ADCs are also analyzed. The analysis shows that the nonidealities in cascaded delta-sigma ADCs cause noise leakage, which limits the overall performance of the cascaded modulators. In order to reduce the noise leakage, a novel adaptive compensation technique is proposed. To verify the effectiveness of the proposed compensation techniques, a prototype 2-0 cascaded modulator was designed. Its first stage, a second-order delta-sigma modulator with test signal input circuit, was designed and fabricated in 1.2 ��m CMOS technology. The measurement results show that the noise leakage is reduced effectively by the compensation, and the performance of the cascaded delta-sigma modulator is greatly improved. / Graduation date: 1999