Dans cette thèse, nous abordons la conception des composants d'électronique de puissance, intégrés sur semi-conducteur. Dans cette large problématique, nous nous intéressons plus particulièrement aux méthodes et outils logiciels et numériques pour le dimensionnement technologique et géométrique. Ainsi, nous abordons le dimensionnement en faisant des compromis d'intégration entre la technologie du composant de puissance et les fonctions électriques de ses composants annexes, en prenant en compte la fiabilité de la réalisation technologique en salle blanche et les impacts de l'environnement électronique. Pour cela, nous avons proposé des démarches, méthodes et outils pour repousser les limites existantes de la conception, visant à offrir le support correspondant en terme de « design kit ». Finalement, nous appliquons les méthodes et les démarches choisies et développées, au dimensionnement d'un MOSFET de puissance (VDMOS), pour différents cahiers des charges. / The thesis deals with the design of integrated power electronics components. In this large problematic, the thesis focuses on the methods and numerical and software tools for the geometrical and technological sizing. So, the thesis deals with the sizing carrying out compromises between the technology of a power component and the electrical characteristics of its auxiliary components, taking into account the reliability of the technological making and the impacts of the electronic environment. In this way, approaches, methods and tools are proposed to push away the existing design limits, to offer the corresponding elements for the design kit. Finally, the developed and chosen methods and approaches are applied to the sizing of a power MOSFET (VDMOS) according to several cases of specifications

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Generating ideas and creating prototypes of physical products is a highly non-linear and iterative process. Current tools divide this process into multiple discrete steps with different tools to support each of these steps such as CAD modelling, simulation and fabrication. We believe, design interfaces that combine different steps of the process and create different layers of abstraction depending on the type of the user and where they are in the process can support users in generating more creative ideas and creating better functioning prototypes more efficiently. In order to validate this, we developed three interfaces- a sketch-based ideation tool, a live programming interface to create IoT devices and a design tool to support design and fabrication of hand wearables. The foundation of these design interfaces is the layer of abstraction that allows users to focus on idea generation and converting it into a tangible prototype with little or no technical knowledge, and a continuous visual feedback that guides the user to make necessary changes to improve their design. The three tools were evaluated through user testing for supporting creation of different ideas and converting them into functional prototypes.

FPGAs are of interest in the signal processing domain as they provide the opportunity to run algorithms at very high speed. One possible use case is to sort incoming data in a measurement system, using e.g. a histogram method. Developing code for FPGA applications usually requires knowledge about special languages, which are not common knowledge in the signal processing domain. High-level synthesis is an approach where high-level languages, as MATLAB or C++, can be used together with a code generation tool, to directly generate an FPGA ready output. This thesis uses the development of a histogram as a test case to investigate the efficiency of three different tools, HDL Coder in MATLAB, HDL Coder in Simulink and System Generator for DSP in comparison to the direct development of the same histogram in Vivado using Verilog. How to write and structure code in these tools for proper functionality was also examined. It has been found that all tools deliver an operation frequency comparable to a direct implementation in Verilog, decreased resource usage, a development time which decreased by 27% (HDL Coder in MATLAB), 45% (System Generator) and 64% (HDL Coder in Simulink) but at the cost of increased power consumption. Instructions for how to use all three tools has been collected and summarised. / I ingångssteget på ett mätsystem är det av intresse att använda en FPGA för att uppnå höga hastigheter på de oundvikliga datafiltrering och sorterings algoritmer som körs. Ett problem med FPGAer är att utvecklingen ställer höga krav på specifik kunskap gällande utvecklingsspråk och miljöer vilket för en person specialiserad inom t.ex. signalbehandling kan saknas helt. HLS är en metodik där högnivåspråk kan användas för digital design genom att nyttja ett verktyg för automatgenerering av kod. I detta arbete har utveckling av ett histogram använts som testfall för att utvärdera effektivitet samt designmetodik av tre olika HLS verktyg, HDL Coder till MATLAB, HDL Coder till Simulink och System Generator for DSP. Utvecklingen i dessa verktyg har jämförts mot utvecklingen av samma histogram i Vivado, där språket Verilog använts. Arbetets slutsater är att samtliga verktyg som testats leverar en arbetsfrekvens som är jämförbar med att skriva histogrammet direkt i Verilog, en minskad resursanvändning, utvecklingstid som minskat med 27% (HDL Coder i MATLAB), 45% (System Generator) och 64% (HDL Coder i Simulink) men med en ökad strömförbrukning. En sammanställning av instruktioner för utveckling med hjälp av verktygen har även gjorts.