Digitized by Kansas Correctional Industries

Thesis. 1977. M.Arch.A.S.--Massachusetts Institute of Technology. Dept. of Architecture. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ROTCH. / Includes bibliographical references. / M.Arch.A.S.

Graduation date: 2002

This dissertation investigates diverse techniques to support multithreading in modern high performance processors. The mechanisms studied expand the architecture of a high performance superscalar processor to control efficiently the interaction between software-controlled and hardware-controlled multithreading. Additionally, dynamic speculative mechanisms are proposed to exploit thread-level-parallelism (TLP) and instruction-level-parallelism (ILP) on a Simultaneous Multithreading (SMT) architecture. First, the hybrid multithreaded execution model is discussed. This model combines software-controlled multithreading with hardware support for efficient context switching and thread scheduling. A thread scheduling technique called set scheduling is introduced and its impact on the overall performance is described. An analytical model of the hybrid multithreaded execution is developed and validated by simulation. Through stochastic simulation, we find that the application of the hybrid multithreaded execution model results in higher processor utilization than traditional software-controlled multithreading. Next, in the main part of this dissertation, a new architecture is proposed: the Dynamic Simultaneous Multithreading (DSMT) processor. In this architecture, multiple threads are identified and created speculatively at runtime without compiler help. Subsequently, a SMT processor core executes those threads. The performance of a DSMT processor was evaluated with a new execution-driven simulator developed specifically for the purpose. Our experimental results based on simulation show that DSMT architecture has very good potential to improve SMT processor's performance when there is only a single task available for execution. / Graduation date: 2003

The most accurate method for performing analog signal processing in MOS (metal-oxide-semiconductor) integrated circuits is through the use of switched-capacitor circuits. A switched-capacitor circuit operates as a discrete-time signal processor. These circuits have been used in a variety of applications, such as filters, gain stages, voltage-controlled oscillators, and modulators. A switched-capacitor circuit contains operational amplifiers (opamps), capacitators, switches, and a clock generator. Capacitors are used to define the state variables of a system. They store charges for a defined time interval, and determine the state variables as voltage differences. Switches are used to direct the flow of charges and to enable the charging and discharging of capacitors. Nonoverlapping clock signals control the switches and allow charge transfer between the capacitors. Opamps are used in order to perform high-accuracy charge transfer from one capacitor to another. The goal of this research is to design and explore future low-voltage switched-capacitor circuits, which are crucial for portable devices. Low-voltage operation is needed for two reasons: making reliable and accurate systems compatible with the submicron CMOS technology and reducing power consumption of the digital circuits. To this end, three different switched-capacitor integrators are proposed, which function with very low supply voltages. One of these configurations is used to design a lowpass ����� modulator for digital-audio applications. This modulator is fabricated and tested demonstrating 80 dB dynamic range with a 1-V supply voltage. The second part of this research is to show that these low-voltage circuits are suitable for modern wireless communication applications, where the clock and signal frequencies are very high. This part of the research has focused on bandpass analog-to-digital converters. Bandpass analog-to-digital converters are among the key components in wireless communication systems. They are used to digitize the received analog signal at an intermediate center frequency. Such converters are used for digital FM or AM radio applications and for portable communication devices, such as cellular phones. The main block, in these converters, is the resonator, which is tuned to a particular center frequency. A resonator must be designed such that it has a sharp peak at a specific center frequency. However, because of circuit imperfections, the resonant peak gain and/or the center frequency are degraded in existing architectures. Two novel switched-capacitor resonators were invented during the second part of this research. These resonators demonstrate superior performance as compared to previous architectures. A fourth-order low-voltage bandpass ����� modulator, using one of these resonators, has been designed. / Graduation date: 2002

Reliable controller designs have been developed in this thesis for a number of finite-horizon and infinite-horizon problems with possibly non-zero initial conditions. These reliable controllers assure that system stability and system performance will be maintained despite certain system faults. The performance measure used in this thesis is an "H[subscript ���]-like norm", which is an induced two-norm from all exogenous signals and initial conditions to the regulated output and final states. Controller designs and existence conditions are presented for a reliable controller for faults in any pre-selected subset of actuators or sensors. Also, controller designs and an existence condition are presented for a reliable controller for any single sensor or actuator fault using sensor and actuator redundancy. / Graduation date: 1999

Basic operation, as well as successful development, of the Brush less Doubly-fed Machine (BDFM) has been documented, and research has turned from proof of concept and early development to the more practical direction of increased manufacturability to prove industrial viability. Previous research centered on using standard induction motor stators along with a manufactured BDFM rotor. The more recent efforts center around a ground up design of an optimized BDFM prototype system including a custom converter, a custom die-cast rotor, and a custom stator, all designed specifically for a BDFM system. This paper presents the design process involved in the development of the rotor and stator of a pre-production optimized 5 hp BDFM with a die-cast rotor, from the initial evaluation of the desired specifications to design, simulation, construction, and finally to testing. Using the results of the 5 hp BDFM design, a 15 hp BDFM was designed and manufactured, and the results of that effort are included in this paper as well. This complete process, from design to testing, enables a closed loop analysis of the design techniques and tools used; the successes of the design can be affirmed and the shortcomings identified and corrected. While the primary goal of this paper is to produce two successful BDFM prototypes, the secondary goal is to improve the BDFM design process. / Graduation date: 1998

Mountain bike suspension forks have been developed to reduce the accelerations transmitted to the rider. However, the effectiveness of suspension forks has not been systematically investigated. It was the goal of this project to quantify the amount of impact acceleration damping afforded by three stiffness settings of suspension forks compared to rigid mountain bike forks. Seven experienced mountain bike riders gave their informed consent to participate in the study. The subjects coasted down a ramp and impacted a bump at 5.4 m/s located about 2.3 m past the ramp end. Accelerometers were placed on the axle and frame of the bicycle which was fitted with either a rigid fork (FR) or suspension forks set on soft (F1), medium (F3), or firm (F6) stiffness. Bumps were either small (B1), medium (B2) or large (B3). Accelerometer data were telemetered to a computer, sampled at 1000 Hz and smoothed with Butterworth filter with 50 Hz cutoff. Peak acceleration during impact (P1) and landing (P2) as well as the slope of the impact acceleration peak (jerk, J) were extracted from the data and analyzed using a 2 x 3 x 4 repeated measures ANOVA for each of the dependent variables (P1, P2, J), and with linear contrasts as follow-up tests. A significance level of p<.01 was chosen. All forks were found to produce similar impact acceleration (P1) at the axle and frame on the small bump (B1). On larger bumps (B2 and B3), softer suspension forks (F1 and F3) significantly reduced acceleration transmitted to the rider during bump impact (P1), while maintaining significantly higher axle acceleration than other forks (p<.001); Jerk was significantly reduced at the frame compared to the axle for each suspension fork with the larger bumps. Landing impacts (P2) were of similar magnitude for most fork conditions at both the axle and frame. It appears from these data that suspension forks with moderate stiffness may provide the best impact acceleration damping for mountain bikes encountering impacts with characteristics similar to the bumps and velocity used in this study. It is unclear how these results generalize to other conditions encountered while riding. / Graduation date: 1997

The objective of this thesis is to design a high speed digital FIR filter. The inputs of the system come from a Delta-Sigma modulator. This FIR filter takes 1024 inputs, multiplies them with their coefficients and adds the results. The main design task is to take the input data, which are unweighted single-bit binary numbers at 156MHz, multiply each bit with the corresponding coefficient and add them to get a weighted multi-bit output at 20MHz. / Graduation date: 1997

Due to advances in high-density low-cost VLSI and communication technology, digital filtering and signal processing are being widely used for real-time signal processing applications. Given the filter specification, choosing the best filter structure for a given application is not a trivial task. The choice of a particular filter structure depends on many factors such as sensitivity to finite word-length quantization effects, hardware complexity and power consumption. The objective of this thesis is to examine digital IIR (Infinite Impulse Response) filter structures for the VLSI implementation of narrow-band sharp-transition filters. This thesis examines several different digital IIR filter structures; namely cascade form IIR filter, five different digital lattice filters and lattice wave digital filter structures. For fixed-point implementation, the sensitivity, round-off noise properties and the scaling of these filter structures are described and analyzed. These filter structures are compared with respect to the architectural complexity, the sensitivity to coefficient quantization, the round-off noise due to product quantization and the signal dynamic range. Fixed-point implementation simulations using two's-complement arithmetic are carried out for a number of narrow-band sharp-transition digital low-pass filters. / Graduation date: 1995