The first topic of the thesis presents an NTSC digital video decoder which is designed by using two lines delay comb filter to decode the luminance signal (Y) and the chrominance signal (C). The coefficients of the low pass filter are tuned properly to reduce the gate count without losing any original performance of the chroma demodulator. The second topic of the thesis is to propose a method and a circuitry to resolve the out-of-phase problem between the color burst and the sub-carrier in NTSC TV receivers. The feature of the method is that a delay means is inserted which leads to the synchronization of the color burst and the sub-carrier such that the following color demodulator is able to extract right color signals. Besides, the locking of the two signals will be fastened without any extra large circuit cost.

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Complex digital circuits such as microprocessors typically require support circuitry that has traditionally been realized using analog or mixed-signal macros. PLL circuits are used in many integrated applications such as frequency synthesizers and inter-chip communication interfaces. As process technologies advance and grow in complexity, the challenge of maintaining required analog elements and performance for use in circuits such as PLLs grows. Recently, digital PLL (DPLL) has emerged as an alternative to analog PLL to overcome many constraints such as low supply voltage, poor analog transistor behavior, larger area due to integrated capacitor and process variability. However, DPLLs have high deterministic jitter due to quantization noise of time-to-digital converter (TDC) and digitally-controlled oscillator (DCO) and struggle with random jitter of oscillator. In this thesis, hybrid analog/digital proportional/integral control is used to suppress TDC quantization error and digital phase accumulation techniques to mitigate DCO quantization error. VCO phase noise was reduced using an embedded voltage-mode feedback. This feedback loop is implemented by using a switched-C circuit which converts frequency to current. Designed in a 130nm CMOS process, the proposed DPLL generates more than 1GHz output frequency with low input frequency and achieves superior jitter performance compared to conventional DPLL in simulations. / Graduation date: 2013

The high demands on data processing and bandwidth in wireless/wireline communication and aerospace systems have been pushing forward circuit design techniques to their limitations to obtain maximum performances with respect to high operating frequency, low noise, small area, and low power consumption. Clock generators are essential components in numerous circuits, for instance, frequency synthesizers for high speed transceivers, clock sources for microprocessors, noise suppressed zero-delay buffers in system-on-chips (SOCs), and clock and data recovery (CDR) systems. Furthermore, clock generators are required to provide low jitter and high precision clocks in fully integrated image reject receivers and an ultra-wide tunability in time-interleaved applications. We explore several circuit design techniques and implementations of low jitter clock generator in this thesis. Firstly, a low jitter and wide range digital phase-locked loop (DPLL) operating 8 ~ 16 GHz is illustrated using a dual path digital loop filter (DLF). In order to mitigate the phase jitter in the phase detector (PD), we implement the separate loop filter and the output is not affected by the proportional path. For the stable operation, a 4 ~ 8 GHz linear phase interpolator (PI) is implemented in the proportional path. In addition, we design a low phase noise digitally controlled oscillator (DCO) using inductive tuning technique based on switched mutual coupling for wide operating range. The proposed DPLL implemented in 65 nm CMOS technology shows an outstanding figure-of-merit (FOM) over other state-of-art DPLLs in term of root mean square (RMS) and deterministic jitter (DJ). Secondly, we discuss a radiation-hardened-by-design (RHBD) PLL using a feedback voltage-controlled oscillator (FBVCO) in order to reduce DJ due to the radiation attack on the control voltage. Different from a conventional open loop VCO, the proposed FBVCO has a negative control loop and is composed of an open loop VCO, an integrator and a switched-capacitor resistor. Since the input to output of the FBVCO has a low-pass characteristic, any disturbance on the control voltage should be filtered and cannot affect the output phase. We are able to reduce the output frequency variation approximately 75% compared to the conventional PLL when the radiation pulse strikes on the control voltage. The proposed RHBD PLL is implemented in 130 nm and consumes 6.2 mW at 400 MHz operating frequency. Thirdly, a novel adaptive-bandwidth PLL is illustrated to optimize the jitter performance in a wide operating frequency range. We achieve a constant ratio of bandwidth and reference frequency with a closed loop VCO and an overdamping system with a charge pump (CP) current proportional to the VCO frequency for the adaptive-bandwidth technique. The proposed adaptive-bandwidth PLL presents 0.6% RMS jitter over the entire frequency range from 320 MHz to 2.56 GHz, which is 70% smaller than the conventional fixed-bandwidth PLL. Finally, we have developed a new feedback DCO to achieve a linear gain of DCO so that the DPLL can provide stability and a wide operating range in different process variations. Due to the negative feedback loop of the proposed DCO, the feedback DCO presents a linear gain from an input digital word to an output frequency. Moreover, we can control the bandwidth of the feedback DCO to optimize the total output phase noise in DPLL. In simulation, we can obtain 17 MHz/LSB of the peak-to-peak gain of the feedback DCO, which is reduced 96% over the conventional DCO.

With the advancement of CMOS process and fabrication, it has been a trend to maximize digital design while minimize analog correspondents in mixed-signal system designs. So is the case for PLL. PLL has always been a traditional mixed-signal system limited by analog part performance. Around 2000, there emerged ADPLL of which all the blocks besides oscillator are implemented in digital circuits. There have been successful examples in application of Bluetooth, and it is moving to improve results for application of WiMax and ad-hoc frequency hopping communication link. Based on the theoretic and measurement results of existing materials, ADPLL has shown advantages such as fast time-to-market, low area, low cost and better system integration; but it also showed disadvantages in frequency resolution and phase noise, etc. Also this new topic still opens questions in many researching points important to PLL such as tracking behavior and quantization effect. In this thesis, a non-linear phase domain model for all digital phase-locked loop (ADPLL) was established and validated. Based on that, we analyzed that ADPLL phase noise prediction derived from traditional linear quantization model became inaccurate in non-linear cases because its probability density of quantization error did not meet the premise assumption of linear model. The phenomena of bandwidth expansion and in-band phase noise decreasing peculiar to integer-N ADPLL were demonstrated and explained by matlab and verilog behavior level simulation test bench. The expression of threshold quantization step was defined and derived as the method to distinguish whether an integer-N ADPLL was in non-linear cases or not, and the results conformed to those of matlab simulation. A simplified approximation model for non-linear integer-N ADPLL with noise sources was established to predict in-band phase noise, and the trends of the results conformed to those of matlab simulation. Other basic analysis serving for the conclusions above covered: ADPLL loop dynamics, traditional linear theory and its quantitative limitations and numerical analysis of random number. Finally, a present measurement setup was demonstrated and the results were analyzed for future work.

Un microscope à force atomique (AFM) est utilisé pour caractériser des matériaux isolant ou semi-conducteur avec une résolution pouvant atteindre l'échelle atomique. Ce microscope est constitué d'un capteur de force couplé à une électronique de contrôle pour pouvoir correctement caractériser ces matériaux. Parmi les différents modes (statique et dynamique), nous nous focalisons essentiellement sur le mode dynamique et plus particulièrement sur le fonctionnement sans contact à modulation de fréquence (FM-AFM). Dans ce mode, le capteur de force est maintenu comme un oscillateur harmonique par le système d'asservissement. Le projet ANR Pnano2008 intitulé : ”Cantilevers en carbure de silicium à piézorésistivité métallique pour AFM dynamique à très haute fréquence" a pour objectif d'augmenter significativement les performances d'un FM-AFM en développant un nouveau capteur de force très haute fréquence. Le but est d'augmenter la sensibilité du capteur et de diminuer le temps nécessaire à l'obtention d'une image de la surface du matériau. Le système de contrôle associé doit être capable de détecter des variations de fréquence de 100mHz pour une fréquence de résonance de 50MHz. Etant donné que les systèmes présents dans l'état de l'art ne permettent pas d'atteindre ces performances, l'objectif de cette thèse fut de développer un nouveau système de contrôle. Celui-ci est entièrement numérique et il est implémenté sur une carte de prototypage basée sur un FPGA. Dans ce mémoire, nous présentons le fonctionnement global du système ainsi que ses caractéristiques principales. Elles portent sur la détection de l'écart de fréquence de résonance du capteur de force. / An atomic force microscope (AFM) is used to characterize insulating materials or semiconductors with a resolution up to the atomic length scale. The microscope includes a force sensor linked to a control electronic in order to properly characterize these materials. Among the various modes (static and dynamic), we focus mainly on the dynamic mode and especially on the frequency modulation mode (FM-AFM). In this mode, the force sensor is maintained as a harmonic oscillator by the servo system. The research project ANR Pnano2008 entitled: "metal piezoresistivity silicon carbide cantilever for very high frequency dynamic AFM" aims to significantly increase the performance of a FM-AFM by developing new very high frequency force sensors. The goal is to increase the sensitivity of the sensor and to decrease the time necessary to obtain topography images of the material. The control system of this new sensor must be able to detect frequency variations as small as 100mHz for cantilevers with resonance frequencies up to 50MHz. Since the state-of-the-art systems doe not present these performances, the objective of this thesis was to develop a new control system. It is fully digital and it is implemented on a FPGA based prototyping board. In this report, we present the system overall functioning and its main features which are related to the cantilever resonant frequency detection. This detection is managed by a phase locked loop (PLL) which is the key element of the system.

Following the rise of Internet of Things (IoT), or just the technological advancements and expectations in a world where the things are or will be connected, new demands are put on Integrated Circuit (IC) for wireless connectivity. The use cases seem endless; smart home, healthcare, entertainment, and science are all areas that can benefit from connectivity of low power electronics. But there are obstacles to overcome. Meeting the specifications, especially the phase noise requirements of modern high-speed wireless standards can be a challenge for devices that run on low supply voltages and are allowed only very limited power consumption. The focus of this thesis is the exploration of modern LC-oscillator architectures for RF-transceivers, and the design and post-layout evaluation of a Digitally Controlled Oscillator (DCO) intended to be used in an All-Digital Phase Locked Loop (ADPLL) in a 22 nm FD-SOI process. The DCO specifications are set by an ADPLL for the Wi-Fi 6 (MCS 11) standard. The ADPLL is replacing the blocks that are usually implemented as noise-sensitive analog components with more robust digital blocks that are easier to integrate with baseband- and digital-circuitry. A dual-core class-C oscillator with a dynamic-biasing circuit is proposed and designed to meet the specification of -121 dBc/Hz phase noise at a 1 MHz offset from 7.8 GHz, a –7.18.6 GHz tuning range, and a frequency resolution of at most 35 kHz around 7.8 GHz. The phase noise specification is met; a phase noise of -121 dBc/Hz at the 1 MHz offset from 7.8 GHz is achieved in post-layout simulation along with a Figure of Merit (FoM) of 189.9, and an average tracking frequency step of 5.8 MHz. The tuning range specification was not met, but it is reasonable to believe that the specified range can be met after some redesign of the capacitor banks. Further work will be required. / Till följd av tillväxten inom Internet of Things (IoT), eller bara de teknologiska framgångar och förväntningar på en värld där dem flesta saker är eller kommer att bli uppkopplade, ställs nya krav på Integrated Circuit (IC)-komponenter för trådlös uppkoppling. Tillämningsområdena är oändliga; smart home, sjukvård och hälsa, underhållning och forskning är områden som som kan dra nytta av nya uppkopplingsmöjligheter med extremt strömsnål elektronik. Att leva upp till specifikationerna för moderna trådlösa höghastighetsuppkopplingar, speciellt när det kommer till fasbrus, kan dock vara en utmaning för enheter som måste klara sig med en väldigt begränsad effektåtgång. Fokus för denna avhandling är design och utvärdering på schematik och layout-nivå av en Digitally Controlled Oscillator (DCO) för en 22 nm Fully Depleted Silicon-On-Insulator (FD-SOI)-process avsedd att klara specifikationen satt av en given All-Digital Phase Locked Loop (ADPLL) för Wi-Fi 6 (MCS 11) standarden. En DCO och ADPLL ersätter block som tidigare tillämpats som analoga bruskänsliga komponenter med robustare digitala komponenter som är enklare att integrera med bas-band och digital logik-kretsar. En dubbelkärnig klass-C DCO med en dynamisk biaskrets föreslås för att nå kravet på fasbrus på maximalt -121 dBc/Hz mätt vid 1 MHz från en frekvens på 7.8 GHz, med ett frekvensomfång 7.1-8.6 GHz och en frekvensupplösning under 35 kHz. Fasbruset vid denna 1 MHz från 7.8 GHz uppmättes i simulering till -121 dBc/Hz, och en Figure of Merit (FoM) på 189.9 har uppnåtts, samt en genomsnittlig frekvensupplösning på 5.8 MHz nära 7.8 GHz. Designen klarar inte av att möta kraven på frekvensomfång, men det är sannolikt att en liknande design kan möta specifikationen efter ytterligare revision. Ytterligare arbete krävs.