The aim of this thesis is introduce readers to the basics of digital frequency synthesis and design of direct digital synthesizer with circuit AD9951 by Analog Devices. The device will be controlled from a PC via RS232. The device will work with internal oscillator, with the ability to connect an external frequency standard.

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The aim of this thesis is introduce readers to the basics of digital frequency synthesis and design of direct digital synthesizer with circuit AD9951 by Analog Devices. The device will be controlled from a PC via USB. The device works with internal oscillator, with the ability to connect an external frequency standard of 10 MHz. On input is frequency doubler with transistor. Outpu signal is filtered by low-pass filter and amplified by monolitic amplifier ERA-3+.

This thesis describes the theoretical development, design, and implementation of a novel measurement system, called a Sampling Swept Time Delay Short Pulse (SSTDSP) wireless channel sounder, capable of real time in field performance characterization of high speed fixed wireless links. The SSTDSP sounder has been designed to provide vital performance metrics for fixed point high data rate applications in the 28 GHz LMDS band at a fraction of the cost and complexity of existing wideband channel sounders. The SSTDSP sounder monitors the behavior of the LMDS channel by sampling the impulse response of the channel in real time. This digitized impulse response is used to assemble a power delay profile and render real-time channel performance metrics such as the mean excess delay, RMS delay spread, maximum excess delay for a given multipath threshold, and coherence bandwidth. The SSTDSP sounder is capable of recording these metrics through three modes of operation - continuous channel monitoring, single instant channel snapshot, or data logging. Swept time delay time dilation processing is combined with precise sample and hold gating to reduce the analog to digital converter sampling rate required to digitize the nanosecond short pulses from 2 Gsps to 1 Msps, while retaining the required effective Nyquist sampling rate of 2 Gsps. This dramatically reduces the memory, digital signal processing, and data logging storage requirements as well as the overall cost of the sounder system. The thesis presents the theory behind channel sounding and discusses whether there is a "bounce path" available to LMDS. Several existing channel sounding methods are compared for this application. A number of specific design and performance criteria from each of these methods are synthesized to produce the Sampling Swept Time Delay Short Pulse Sounder architecture. The design and implementation process used to realize the SSTDSP sounder is presented, including a system overview, module details, and algorithm development details. A calibration and measurement test procedure is outlined and system verification results are presented. Current work in progress on the test platform and future improvements to the modular system are outlined, as well as conclusions and future implications of the system. / Master of Science

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / In this paper design and development of a PC- Based S- Band Down Converter/ FM Telemetry Receiver are discussed. With the advent of Direct Digital Synthesis (DDS) & Phase Locked Loop (PLL) technology, availability of GaAs & Silicon MMICs, Coaxial Resonator Oscillator (CRO), SAW Oscillator, SAW Filters and Ceramic Filters, realisation of single card PC- Based Down Converter and Telemetry Receiver has become a reality. With the availability of Direct Digital Synthesis and Phase Locked Loop devices having microprocessor bus compatibility, opens up many application in Telemetry and Telecommunications. In this paper design of local oscillator based on hybrid DDS & PLL technique, Coaxial Resonator Oscillator and Front-end are discussed in detail.

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / Aerospace Report No. TOR-0059(6110-01)-3, section 1.3.3 outlines the design and performance requirements of SGLS (Space Ground Link Subsystem) uplink services equipment. This modulation system finds application in the U.S. Air Force satellite uplink commanding system. The SGLS signal generator is specified as an FSK (Frequency Shift Keyed)/AM (Amplitude Modulation)/PM (Phase Modulation) sub-carrier modulator. GDP Space Systems has implemented, on a single 6U-VME card, a SGLS signal generator. The modulator accepts data from several possible sources and uses the data to key one of three FSK tone frequencies. This ternary FSK signal is amplitude modulated by a synchronized triangle wave running at one half the data rate. The FSK/AM signal is then used to phase modulate a tunable HF (High-Frequency) sub-carrier. A digital design approach and the availability of integrated circuits with a high level of functionality enabled the realization of a SGLS signal generator on a single VME card. An analog implementation would have required up to three rack-mounted units to generate the same signal. The digital design improve performance, economy and reliability over analog approaches. This paper describes the advantages of a digital FSK/AM/PM modulation method, as well as DDS (Direct Digital Synthesis) and digital phase-lock techniques.

The purpose of this semestral project is to explain the basic issues of simple digital modulations through the creation of simple digital modulations using direct digital synthesis. It begins with a short review of digital modulation theory and the theory about direct digital synthesis. All the technical documentation is attached, including schematics and boards of functional modulator.

This diploma thesis concerns with analysis and dividing of frequency synthesizers and design of DDS, PLL synthesizers. Base types of frequency synthesizers are described including differences between methods of their operation. Base circuits of both – DDS and PLL synthesizers and other important circuits are described in details at design part of this thesis. Design of DDS and PLL synthesizer is described in particular sections. Both synthesizers are directly realized and stand-alone control applications are created. PLL synthesizer is also ready to control thru Agilent VEE program environment. Particular example application is designed in Agilent VEE. This application is used as basis of attached lab project.

Lead acid batteries are widely used in domestic, industrial and automotive applications. Even after lot of advancements in battery technologies, lead acid cells are still in use because of their high capacity and low cost. To use any battery effectively, first we should be able to identify the available capacity or State of Charge (SoC). There are many techniques available to measure SoC of a lead acid battery. One such unique method is to measure the capacity using eddy current sensors. This method is unique because it is non-obtrusive and online. Eddy current sensors (ECS) are wire wound inductors which work on the principle of electromagnetic induction. Eddy currents are the currents generated on a conductive material when it is kept in a varying magnetic. Eddy current sensors generate varying magnetic eldest and will be able to identify the properties of conductive materials like thickness, conductivity, material composition etc. Also they can be used as proximity sensors. Lead acid batteries use lead metal as cathode. Upon usage(discharge) the lead metal converts to lead sulfate and revert back to lead after charging. These changes in lead electrode can be monitored using eddy current sensors. The impedance of an eddy current sensor will change when it is kept close to the lead electrode when the battery is charging or discharging. These impedance parameters can be monitored to determine the battery SoC. When lead is deposited on cathode, there will be more eddy current loss in the target and the total resistance of coil increases. On the other hand, when lead is deposited on the electrode because of increase in the magnitude of eddy currents which oppose the source magnetic, the total inductance of coil decreases. We can observe exactly opposite behaviour of coil resistance and inductance when the lead electrode is converted to less conductive lead sulfate. There is a lot of research on using ECS to measure SoC of lead acid batteries and there are still many challenges to be addressed. First we have explained about different circuit designs we have used to monitor the battery capacity using eddy current sensors. After that, we have explained about our complete experimental setup and the procedure to measure the sensor parameters using the setup. Then, we have discussed about different issues involved in the eddy current sensing based state of charge measurement. Eddy current sensors are affected by temperature variations. We have studied the coil resistance behaviour with temperature at different frequencies using simulations and experiments. We have obtained the conditions for linear variation of coil resistance with temperature. The measured temperature compensation scheme is applied and the results are discussed. We have also modified the measurement system design in order to minimize the lift o errors. We have used a metallic clamp structure to minimize the lift o errors. We have used finite element analysis based simulations to study different design parameters and their effect on the sensitivity of eddy current sensor. We have created 2D eddy current models and the sensitivity of coil resistance is computed by changing the coil dimensions and the core permeability. We have also performed error analysis and computed the error due to the tilt angle shift between coil and electrode. We have also computed the error due to the internal heating of battery. We have also studied the effect of acid strati cation on state of charge for both sealed and hooded batteries. We have proposed a multi coil method to minimize the errors in SoC measurement due to acid strati cation for Flooded type batteries. We have used finite element analysis based simulations to compute the error due to acid strati cation by increasing the number of coils. Finally we have derived the equation for electrode Q factor using the transformer model of eddy current sensor. The derived Q factor equation is then used to study the aging of lead acid batteries both by using experiments and simulations. Finally we have explained a detail procedure to measure the state of charge(SoC) and state of health(SoH) of a hooded lead acid battery using eddy current sensing method.

This work deals with frequency generators based on the direct digital synthesis method DDS. Basic principles and attributes of the frequency generator DDS are explained. The text describes parameters influencing and defining a quality of the generated signal. The list of available integrated circuits realizing the direct digital synthesis is mentioned. A construction of the DDS generator with a device AD9954 and the generator control are described. At the end of the work, the function and parameters of the designed generator are verified.