With the trends of fast edge rates, high clock frequencies, and low voltage levels for the high-speed digital computer systems, the ground bounce noise (GBN) or simultaneously switching noise (SSN) on the power/ground planes is becoming one of the major challenges for designing the high-speed circuits. In order to analyze the impact of the GBN on signal integrity (SI) and electromagnetic interference (EMI), an accurate and efficient modeling approach that considers the active devices and passive interconnects is required. This thesis focuses on two points. One is developing modeling approaches for analyzing the GBN effects, and the other is proposing solutions to reduce it. First, based on the FDTD algorithm several efficient modeling approaches including equivalent current-source method (ECSM), Kirchoff surface integral representation (KSIR), and slot-corrected 2D-FDTD are developed. After that, a power/ground-planes design for efficiently eliminating the GBN in high-speed digital circuits is proposed by using low-period coplanar electromagnetic bandgap (LPC-EBG) structure. Its extinctive behaviors of low radiation and broadband suppression of the GBN is demonstrated numerically and experimentally. Good agreements are seen.

This thesis focuses on the modeling and solutions of the simultaneous switching noise (SSN) problems in the power delivery networks (PDN) of high-speed digital circuit packages. An efficient numerical approach based on two-dimension (2D) finite-difference time-domain (FDTD) method combined with the lumped circuit model of the interconnection is proposed to model the PDN of a package and PCB. Based on this approach, the mechanism of noise coupling between package and PCB can be analyzed. In addition, a novel photonic crystal power layer (PCPL) design for the PDN of the package or PCB is proposed to suppress the SSN. The periodic High-Dk material is embedded into the substrate layer between the power and ground planes. Both modeling and measurement demonstrate the PCPL can form a wide stopband well with excellent suppression of the SSN propagation in the substrate and the corresponding electromagnetic interference (EMI).

This master thesis describes stochastic optimization algorithms inspired in nature that use population of individuals - evolutionary algorithms. Genetic programming and its variant - cartesian genetic programming is described in a greater detail. This thesis is further focused on the analysis and visualization of digital circuit evolution records. Existing tools for visualization of the circuit evolution were analysed, but because no suitable tool allowing complex analysis of the circuit evolution was found, a new set of functions was proposed and the principles of a new tool were formulated. These functions were implemented in form of an interactive GUI application in Java programming language. The application was described in detail and then used for analysis of digital circuit evolution records.

The aim of this diploma thesis is to survey the area of multiobjective genetic algorithms and cartesian genetic programming. In detail the NSGAII algorithm and integration of multiobjective optimalization into cartesian genetic programming are described. The method of multiobjective CGP was tested on selected problems from the area of digital circuit design.

This thesis deals with evolutionary design of the digital circuits performed by a cartesian genetic programing and optimization by a coevolution. Algorithm coevolves fitness predictors that are optimized for a population of candidate digital circuits. The thesis presents theoretical basis, especially genetic programming, coevolution in genetic programming, design of the digital circuits, and deals with possibilities of the utilization of the coevolution in the combinational circuit design. On the basis of this proposal, the application designing and optimizing logical circuits is implemented. Application functionality is verified in the five test tasks. The comparison between Cartesian genetic programming with and without coevolution is considered. Then logical circuits evolved using cartesian genetic programming with and without coevolution is compared with conventional design methods. Evolution using coevolution has reduced the number of evaluation of circuits during evolution in comparison with standard cartesian genetic programming without coevolution and in some cases is found solution with better parameters (i.e. less logical gates or less delay).

Lorsqu'un enseignant veut évaluer le savoir-faire des apprenants à l'aide d'un logiciel, il utilise souvent les systèmes Tutoriels Intelligents (STI). Or, les STI sont difficiles à développer et destinés à un domaine pédagogique très ciblé. Depuis plusieurs années, l'utilisation d'algorithmes de classification par apprentissage supervisé a été proposée pour évaluer le savoir des apprenants. Notre hypothèse est que ces mêmes algorithmes vont aussi nous permettre d'évaluer leur savoir-faire. Notre domaine d'application étant l'électronique numérique, nous proposons une mesure de similarité entre schémas électroniques et une bas d'apprentissage générée automatiquement. cette base d'apprentissage est composées de schémas électroniques pédagogiquement étiquetés "bons" ou "mauvais" avec des informations concernant le degré de simplification des erreurs commises. Finalement, l'utilisation d'un algorithme de classification simple (les k plus proches voisins) nous a permis de faire une évaluation des schémas électroniques dans la majorité des cas. / When a teacher wants to evaluate the know-how of the learners using a software, he often uses Intelligent Tutorial Systems (ITS). However, those systems are difficult to develop and intended for a very targeted educational domain. For several years, the used of supervised classification algorithms was proposed to estimate the learners' knowledge. From this fact, we assume that the same kinf of algorithms can help to adress the learners' know-how evaluation. Our application field being digital system design, we propose a similarity measure between digital circuits and instances issued from an automatically generated database. This database consists of electronic circuits pedagogically labelled "good" or "bad" with information concerning the simplification degrees or made mistakes. Finally, the use of a simple classification algorithm (namely k-nearest neighbours classifier) allowed us to achieve a circuit's evaluation in most cases.

This thesis deals with the possibilities of digital circuit test optimization using multifunctional logic gates. The most important part of this thesis is the explanation of the optimization principle, which is also described by a formal mathematical apparatus. Based on this apparatus, the work presents several options. The optimization of testability analogous to inserting test points and  simple methodology based on SCOAP is shown. The focus of work is a methodology created to optimize circuit tests. It was implemented in the form of software tools. Presented in this work are the results of using these tools to reduce the test vectors volume while maintaining fault coverage on various circuits, including circuits from the ISCAS 85 test set. Part of the work is devoted to the various principles and technology of creating multifunctional logic gates. Some selected gates of these technologies are subject to simulations of electronic properties in SPICE. Based on the principles of presented methodology and results of multifunctional gates simulations, analysis of various problems such as validity of the modified circuit test and the suitability of each multifunctional gate technology for the methodology was also made. The results of analysis and experiments confirm it is possible for the multifunctional logic gate to optimize circuit diagnostic properties in such a way that has achieved the required circuit test parameter modification with minimum impact on the quality and credibility of these tests.

Integrated circuit development is an industry-driven high-risk high-stakes environment. The time from the concept of a new transistor technology to the market-ready product is measured in decades rather than months or years. This increases the risk for any company endeavouring on the journey of driving a new concept. Additionally to the return on investment being in the far future, it is only to be expected at all in high volume production, increasing the upfront investment. What makes the undertaking worthwhile are the exceptional gains that are to be expected, when the production reaches the market and enables better products. For these reasons, the adoption of new transistor technologies is usually based on small increments with foreseeable impact on the production process. Emerging semiconductor device development must be able to prove its value to its customers, the chip-producing industry, the earlier the better. With this thesis, I provide a new approach for early evaluation of emerging reconfigurable transistors in reconfigurable digital circuits. Reconfigurable transistors are a type of MOSFET that features a controllable conduction polarity, i.e., they can be configured by other input signals to work as PMOS or NMOS devices. Early device and circuit characterisation poses some challenges that are currently largely neglected by the development community. Firstly, to drive transistor development into the right direction, early feedback is necessary, which requires a method that can provide quantitative and qualitative results over a variety of circuit designs and must run mostly automatic. It should also require as little expert knowledge as possible to enable early experimentation on the device and new circuit designs together. Secondly, to actually run early, its device model should need as little data as possible to provide meaningful results. The proposed approach of this thesis tackles both challenges and employs model checking, a formal method, to provide a framework for the automated quantitative and qualitative analysis. It pairs a simple transistor device model with a charge transport model of the electrical network. In this thesis, I establish the notion of transistor-level reconfiguration and show the kinds of reconfigurable standard cell designs the device facilitates. Early investigation resulted in the discovery of certain modes of reconfiguration that the transistor features and their application to design reconfigurable standard cells. Experiments with device parameters and the design of improved combinational circuits that integrate new reconfigurable standard cells further highlight the need for a thorough investigation and quantification of the new devices and newly available standard cells. As their performance improvements are inconclusive when compared to established CMOS technology, a design space exploration of the possible reconfigurable standard cell variants and a context-aware quantitative analysis turns out to be required. I show that a charge transport model of the analogue transistor circuit provides the necessary abstraction, precision and compatibility with an automated analysis. Formalised in a DSL, it enables designers to freely characterise and combine parametrised transistor models, circuit descriptions that are device independent, and re-usable experiment setups that enable the analysis of large families of circuit variants. The language is paired with a design space exploration algorithm that explores all implementation variants of a Boolean function that employs various degrees and modes of reconfiguration. The precision of the device models and circuit performance calculations is validated against state-of-the-art FEM and SPICE simulations of production transistors. Lastly, I show that the exploration and analysis can be done efficiently using two important Boolean functions. The analysis ranges from worst-case measures, like delay, power dissipation and energy consumption to the detection and quantification of output hazards and the verification of the functionality of a circuit implementation. It ends in presenting average performance results that depend on the statistical characterisation of application scenarios. This makes the approach particularly interesting for measures like energy consumption, where average results are more interesting, and for asynchronous circuit designs which highly depend on average delay performance. I perform the quantitative analysis under various input and output load conditions in over 900 fully automated experiments. It shows that the complexity of the results warrants an extension to electronic design automation flows to fully exploit the capabilities of reconfigurable standard cells. The high degree of automation enables a researcher to use as little as a Boolean function of interest, a transistor model and a set of experiment conditions and queries to perform a wide range quantitative analyses and acquire early results.:1 Introduction 1.1 Emerging Reconfigurable Transistor Technology 1.2 Testing and Standard Cell Characterisation 1.3 Research Questions 1.4 Design Space Exploration and Quantitative Analysis 1.5 Contribution 2 Fundamental Reconfigurable Circuits 2.1 Reconfiguration Redefined 2.1.1 Common Understanding of Reconfiguration 2.1.2 Reconfiguration is Computation 2.2 Reconfigurable Transistor 2.2.1 Device geometry 2.2.2 Electrical properties 2.3 Fundamental Circuits 3 Combinational Circuits and Higher-Order Functions 3.1 Programmable Logic Cells 3.1.1 Critical Path Delay Estimation using Logical Effort Method 3.1.2 Multi-Functional Circuits 3.2 Improved Conditional Carry Adder 4 Constructive DSE for Standard Cells Using MC 4.1 Principle Operation of Model Checking 4.1.1 Model Types 4.1.2 Query Types 4.2 Overview and Workflow 4.2.1 Experiment setup 4.2.2 Quantitative Analysis and Results 4.3 Transistor Circuit Model 4.3.1 Direct Logic Network Model 4.3.2 Charge Transport Network Model 4.3.3 Transistor Model 4.3.4 Queries for Quantitative Analysis 4.4 Circuit Variant Generation 4.4.1 Function Expansion 5 Quantitative Analysis of Standard Cells 5.1 Analysis of 3-Input Minority Logic Gate 5.1.1 Circuit Variants 5.1.2 Worst-Case Analysis 5.2 Analysis of 3-Input Exclusive OR Gate 5.2.1 Worst-Case Analysis 5.2.2 Functional Verification 5.2.3 Probabilistic Analysis 6 Conclusion and Future Work 6.1 Future Work A Notational conventions B prism-gen Programming Interfaces Bibliography Terms & Abbreviations

This dissertation focuses on design and implementation of a fully-integrated SRAM-based arbitrary waveform generator for analog signal processing applications in a CMOS technology. The dissertation consists of two parts: Firstly, a fully-integrated arbitrary waveform generator for a multi-resolution spectrum sensing of a cognitive radio applications, and an analog matched-filter for a radar application and secondly, low-power techniques for an arbitrary waveform generator. The fully-integrated low-power AWG is implemented and measured in a 0.18-¥ìm CMOS technology. Theoretical analysis is performed, and the perspective implementation issues are mentioned comparing the measurement results. Moreover, the low-power techniques of SRAM are addressed for the analog signal processing: Self-deactivated data-transition bit scheme, diode-connected low-swing signaling scheme with a short-current reduction buffer, and charge-recycling with a push-pull level converter for power reduction of asynchronous design. Especially, the robust latch-type sense amplifier using an adaptive-latch resistance and fully-gated ground 10T-SRAM bitcell in a 45-nm SOI technology would be used as a technique to overcome the challenges in the upcoming deep-submicron technologies.

This project focuses on a prototype system architecture which integrates features of an event-driven gate-level simulator and features of the multiple expert system architecture, HEARSAY-II. Combining artificial intelligence and simulation techniques, a knowledge-based simulator was designed and constructed to model non-standard circuit behavior. This non-standard circuit behavior is amplified by advances in integrated circuit technology. Currently available digital circuit simulators can not simulate this behavior. Circuit designer expertise on behavioral phenomena is used in the expert system to guide the base simulator by manipulating its events to achieve the desired behavior.