Thesis (M.S.)--University of Wisconsin--Madison, 1968. / eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references.

Thesis (M.S.)--University of Wisconsin--Madison, 1964. / eContent provider-neutral record in process. Description based on print version record. Bibliography: l. [95]-96.

Thesis (M.S.)--University of Wisconsin--Madison, 1961. / Typescript. eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references.

Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.

Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.

No description available.

The design of a 16 word 25 bit tunnel-diode memory is described. The memory is word organized and employs destructive readout, the current change of state of the tunnel diodes being sensed. This arrangement requires only a resistor and tunnel diode for each bit stored. The driver circuits for the memory serve three functions: 1) to couple into the array the information to be stored, 2) to supply dc biasing to the array and, 3) to sense the current transient on readout. Low impedance circuits are required, and two approaches are examined: the modified White emitter follower and the transformer coupled emitter follower. The former employs negative feedback to decrease its input impedance, while the latter employs a broadband transformer. The design of the modified White circuit necessitates an examination of the properties of transistors in the 100 Megacycle frequency range. The characteristics of a few high frequency transistors are shown. The transformer coupled circuit depends on the properties of the broadband transformer. These transformers are examined and a design technique for various current ratios is given. Two sets of experimental results are described using 2X2 arrays to simulate the 16X25 memory. One employs 5 ma tunnel diodes, and the other 1 ma tunnel diodes. Using the 1 ma array with transformer input, successful operation with write pulses 10 nanoseconds wide is demonstrated. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

A display system for a polarity-coincidence digital correlator is described in this thesis. The display of normalized statistical estimates of the computer occurs whenever the sample size equals 2ⁿ ( n = 1, 2, …, 18). This allows one to visually determine convergence of the estimates as they are being computed. A brief description of the correlator is included, permitting the reader to relate more easily its output information and control functions with the display system. The order of magnitude of errors introduced by sampling fluctuations and by the digital-to-analogue conversion is shown to be less than 2% of full scale at the output of the monitoring system (sample size =2¹⁸ ), with about 95% confidence limits assigned to the standard deviation of the correlogram. Displays of the estimates stored in the memory of the computer are illustrated for various modes of operation of the correlator. In particular, it is shown how the display system facilitates observation of the rate of convergence of correlation estimates towards their final values. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

Small special purpose digital computers (SPDG) could be used to control processes for which the cost of general purpose digital, computers is prohibitive. This thesis describes a SPDC to optimize a process for which an exact mathematical model does not exist. The SPDC could use any of the empirical or trial and error methods originally designed for hand calculations or for use on a large general purpose digital computer. The methods discussed in this thesis are gradient search, direct search and random search. The overall operation of a SPDC is described in detail using logic block symbols. From the knowledge gained in building and testing the computer, improvements in circuitry and search strategy are suggested. The logic and circuitry used in a SPDC depend on the nature of the process to be controlled. This is illustrated in the thesis by the description of the optimization of a flotation process. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

An algorithm is developed for performing parameter estimation on a small-size digital computer. First principles of matrix algebra are used to derive a sequential estimator which computes an estimate of a general parameter array A from an array of measurements Z = HA+V where V is a matrix of zero-mean noise terms. At every stage a new row is adjoined to each of Z, H. and V and a new estimate of A is calculated recursively, with any one of three well-known filtering processes available from the same basic set of recursive equations: a least-squares filter to minimize [ Formula omitted ], a maximum-likelihood filter to maximize [ Formula omitted ] or a maximum- a-posteriori filter to maximize [ Formula omitted ]. Provision is made for starting the filter either with a-priori means and variances of the parameters or with a deterministic "minimum-norm" composition based on the first s measurement rows, s being the number of rows in the parameter array. The algorithm is applied to the problem of identifying the parameters of a discrete model for a linear time-invariant control system directly from sequential observations of the inputs and outputs. Results from computer tests are used to demonstrate properties of the algorithm and the important computer programs are included, along with suggestions for further applications. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate