No description available.

The dynamic performance of control systems can be improved by incorporating carefully designed compensators. Historically, these compensators have been implemented with analog hardware. However, digitally based compensator designs offer far superior advantages; such as no aging, repeatability, etc. The major reason for rejecting the digital approach to compensator design has been cost. With the introduction of the INTEL 2920 4-input, 8-output, real-time signal processing chip (with AD and DA on-board), cost is no longer a barrier. In this research paper, the complete software-hardware 2920 design cycle required to implement a lead-lag control system compensator is illustrated.

Call number: LD2668 .T4 1966 G491 / Master of Science

Typescript (photocopy). / Digitized by Kansas Correctional Industries

This dissertation describes a new performance modelling system, called the Performance Evaluating Virtual Parallel Machine (PEVPM). It uses a novel bottom-up approach, where submodels of individual computation and communication events are dynamically constructed from data-dependencies, current contention levels and the performance distributions of low-level operations, which define performance variability in the face of contention.

Electronic publication; full text available in PDF format; abstract in HTML format. This dissertation describes a new performance modelling system, called the Performance Evaluating Virtual Parallel Machine (PEVPM). It uses a novel bottom-up approach, where submodels of individual computation and communication events are dynamically constructed from data-dependencies, current contention levels and the performance distributions of low-level operations, which define performance variability in the face of contention. Electronic reproduction.[Australia] :Australian Digital Theses Program,2001. xvii, 295 p. : ill., charts (col.) ; 30 cm.

Not available / text

No description available.

No description available.

No description available.