Test and evaluation (TandE) is a critically important step before in-the-field deployment of radio-frequency (RF) hardware in order to assure that the hardware meets its design requirements and specifications. Typically, TandE is performed either in a lab setting utilizing a software simulation environment or through real-world field testing. While the former approach is typically limited by the accuracy of the simulation models (particularly of the anticipated hardware effects) and by non-real-time data rates, the latter can be extremely costly in terms of time, money, and manpower. To build upon the strengths of these approaches and to mitigate their weaknesses, this work presents the development of an FPGA-based TandE tool that allows for real-time pseudo-random aggregate signal generation for testing RF receiver hardware (such as communication receivers, spectrum sensors, etc.). In particular, a framework is developed for an FPGA-based implementation of a test signal emulator that generates randomized aggregate spectral environments containing signals with random parameters such as center frequencies, bandwidths, start times, and durations, as well as receiver and channel effects such as additive white Gaussian noise (AWGN). To test the accuracy of the developed spectrum generation framework, the randomization properties of the framework are analyzed to assure correct probability distributions and independence. Additionally, FPGA implementation decisions, such as bit precision versus accuracy of the generated signal and the impact on the FPGA's hardware footprint, are analyzed.This analysis allows the test signal engineer to make informed decisions while designing a hardware-based RF test system. This framework is easily extensible to other signal types and channel models, and can be used to test a variety of signal-based applications. / Master of Science / Test and evaluation (TandE) is a critically important step before in-the-field deployment of radio-frequency signal hardware in order to assure that the hardware meets its design requirements and specifications. Typically, TandE is performed either in a lab setting utilizing a software simulation or through real-world field testing. While the former approach is typically limited by the accuracy of the simulation models and by slower data rates, the latter can be extremely costly in terms of time, money, and manpower. To address these issues, a hardware-based signal generation approach that takes the best of both methods mentioned above is developed in this thesis. This approach allows the user to accurately model a radio-frequency system without requiring expensive equipment. This work presents the development of a hardware-based TandE tool that allows for real-time random signal generation for testing radio-frequency receiver hardware (such as communication receivers). In particular, a framework is developed for an implementation of a test signal emulator that allows for user-defined randomization of test signal parameters such as frequencies, signal bandwidths, start times, and durations, as well as communications receiver effects. To test the accuracy of the developed emulation framework, the randomization properties of the framework are analyzed to assure correct probability distributions and independence. Additionally, hardware implementation decisions such as bit precision versus quality of the generated signal and the impact on the hardware footprint are analyzed. Ultimately, it is shown that this framework is easily extensible to other signal types and communication channel models.

Digital signal processing systems demand higher computational performance and more operations per second than ever before, and this trend is not expected to end any time soon. Processing architectures must adapt in order to meet these demands. The two techniques most prevalent for achieving throughput constraints are parallel processing and stream processing. By combining these techniques, significant throughput improvements have been achieved. These preliminary results apply to specific applications, and general tools for automation are in their infancy. In this dissertation techniques are developed to automatically generate efficient parallel streaming hardware architectures. / Ph. D. / The algorithms that process data have been getting more complicated requiring more operations in less time. This trend has been going on for many years with no end in sight. Techniques must be developed to allow the processing system to meet these requirements. Assembly line techniques, or stream processing allows multiple stages in which each stage is working on a different piece of data. Increasing the number of assembly lines can further increase the number of operations, but results in large overheads. This dissertation develops automation techniques to reduce these overheads resulting in efficient hardware.

Το αντικείμενο της διδακτορικής διατριβής αφορά στην ανάπτυξη μιας ευέλικτης και επεκτάσιμης αρχιτεκτονικής που θα αξιοποιηθεί στον σχεδιασμό συστημάτων για την διεξαγωγή πειραμάτων από απόσταση. Τα συστήματα αυτά αναφέρονται ως RLs (Remote Laboratories) και επιτρέπουν στους χρήστες να χειρίζονται απομακρυσμένα τον διαθέσιμο εργαστηριακό εξοπλισμό με σκοπό την διεξαγωγή πειραμάτων. Στην διεθνή βιβλιογραφία έχουν καταγραφεί σημαντικές ερευνητικές προσπάθειες που σχετίζονται με την ανάπτυξη RLs σε διάφορα γνωστικά αντικείμενα. Όμως ακόμη και σήμερα δεν έχει υιοθετηθεί από την επιστημονική κοινότητα κάποια κοινά αποδεκτή αρχιτεκτονική για την ανάπτυξη RLs. Αρχικά προτείνεται μια αρχιτεκτονική για την ανάπτυξη RLs η οποία ονομάζεται ARIAL (Architecture of Internet Accessible Laboratories) η οποία είναι ανεξάρτητη από το γνωστικό αντικείμενο των υποστηριζόμενων από απόσταση πειραμάτων. Η συγκεκριμένη αρχιτεκτονική είναι επίσης ανεξάρτητη τόσο από το υλικό (hardware) όσο και από το λογισμικό (software) που θα αξιοποιηθεί για την ανάπτυξη ενός RL. Η ARIAL αποτελείται από δύο δομικά στοιχεία, τον MWS (Main Web Server) και το WS (WorkStation). Ο MWS αναλαμβάνει κυρίως την διαχείριση των χρηστών και των διαθέσιμων WSs. Ενώ τα WSs που συνήθως βρίσκονται σε πολλαπλότητα, αναλαμβάνουν αποκλειστικά την διεξαγωγή των υποστηριζόμενων από απόσταση πειραμάτων. Η επικοινωνία μεταξύ του MWS και των WSs επιτυγχάνεται μέσω μιας βάσης δεδομένων που επιτρέπει την πρόσβαση μέσω διαδικτύου. Επομένως, τα WSs μπορούν να εγκατασταθούν σε οποιαδήποτε γεωγραφική τοποθεσία επιτρέποντας την ανάπτυξη ομοσπονδιακών RLs. Όμως το σημαντικότερο χαρακτηριστικό της προτεινόμενης αρχιτεκτονικής το οποίο συμβάλει αποφασιστικά στην βιωσιμότητα ενός RL, είναι η υποστήριξη από απόσταση πειραμάτων που έχουν σχεδιαστεί και υλοποιηθεί από τους χρήστες. Με στόχο την επιβεβαίωση της ARIAL προτείνεται ένα RL στην ψηφιακή επεξεργασία σήματος με DSPs που ονομάζεται R-DSP Lab (Remote Digital Signal Processors Laboratory). Το R-DSP Lab παρέχει στους χρήστες την δυνατότητα είτε να διεξάγουν ένα από τα προκαθορισμένα από απόσταση πειράματα είτε να επιβεβαιώσουν την ορθή λειτουργία μιας DSP εφαρμογής που ανέπτυξαν οι ίδιοι. Το συγκεκριμένο RL επιτρέπει επίσης την ανάπτυξη από απόσταση πειραμάτων από τους χρήστες. Στην περίπτωση αυτή οι χρήστες εκτός από την DSP εφαρμογή που επιθυμούν, θα πρέπει να υλοποιήσουν και το GUI (Graphical User Interface) που αναλαμβάνει τον απομακρυσμένο έλεγχο της παραπάνω DSP εφαρμογής. Κατά την διεξαγωγή οποιουδήποτε από τα παραπάνω απόσταση πειράματα οι χρήστες μέσω μιας κατάλληλα σχεδιασμένης ιστοσελίδας έχουν την δυνατότητα να ελέγχουν απομακρυσμένα τα διαθέσιμα εργαστηριακά όργανα. Στην συνέχεια προτείνεται ένα RL στην ψηφιακή επεξεργασία εικόνας με DSPs που ονομάζεται R-DImPr Lab (Remote Digital Image Processing Laboratory). Το συγκεκριμένο RL επιτρέπει την επιβεβαίωση μιας DSP εφαρμογής που αναπτύχθηκε από τον χρήστη αξιοποιώντας το API (Application Program Interface) του R-DImPr Lab. Η DSP εφαρμογή αναλαμβάνει την ψηφιακή επεξεργασία εικόνων που λαμβάνονται από τον διαθέσιμο αισθητήρα εικόνας. Κατά την διεξαγωγή του από απόσταση πειράματος ο χρήστης μέσω της ιστοσελίδας του RL αφού επιλέξει τις ρυθμίσεις του αισθητήρα εικόνας, έχει την δυνατότητα να παρατηρήσει τόσο στην αρχική όσο και στην επεξεργασμένη εικόνα. Με σκοπό την διεύρυνση των δυνατοτήτων του R-DimPr Lab σχεδιάστηκε και αναπτύχθηκε ένα σύστημα επεξεργασίας εικόνας με DSPs το οποίο παρέχει στους χρήστες την δυνατότητα να διεξάγουν από απόσταση πειράματα ελέγχοντας απομακρυσμένα, τόσο την λειτουργία της αντίστοιχης DSP εφαρμογής όσο και την θέση του αισθητήρα εικόνας. Ο έλεγχος της θέσης του αισθητήρα εικόνας επιτυγχάνεται μέσω ενός μηχανισμού κίνησης που βασίζεται σε δύο βηματικούς κινητήρες και επιτρέπει την περιστροφή του αισθητήρα εικόνας σε δύο άξονες. Επιπρόσθετα, διερευνείται η δυνατότητα ανάπτυξης από απόσταση πειραμάτων στην ψηφιακή επεξεργασία εικόνας με DSPs από τους χρήστες αξιοποιώντας το R-DSP Lab. Τέλος, προτείνεται ένα RL στην αρχιτεκτονική των υπολογιστών που επιτρέπει στους χρήστες να προγραμματίσουν σε assembly μια από τις δύο διαθέσιμες CPUs (Central Processing Units). Κατά την διαδικασία επιβεβαίωσης, αρχικά φορτώνεται στο FPGA (Field Programmable Gate Array) της διαθέσιμης αναπτυξιακής πλατφόρμας η υλοποίηση του συστήματος που βασίζεται στην επιλεγμένη CPU. Στην συνέχεια μέσω του GUI της ιστοσελίδας του προτεινόμενου RL, οι χρήστες έχουν την δυνατότητα να παρατηρήσουν βήμα προς βήμα τις μικρο-λειτουργίες που λαμβάνουν χώρα στην επιλεγμένη CPU κατά την εκτέλεση του προγράμματος. / The subject of this Ph.D. dissertation deals with the development of a flexible and expandable architecture which will be exploited in the design of systems for the conduction of remote experiments. These systems are referred as RLs (Remote Laboratories) and allow the users to handle remotely the available laboratory equipment in order to perform remote experiments. Significant scientific efforts which deal with the development of RLs in several cognitive fields, have been documented in the international literature. However, even today a commonly accepted architecture for the development of RLs has not been adopted by the scientific community. At the beginning, an architecture for the development of RLs which is called ARIAL (ARchitecture of Internet Accessible Laboratories) and is independent of the cognitive field of the supported remote experiments, is proposed. This architecture is also independent of both the hardware and the software which will be utilized for the development of the corresponding RL. The ARIAL consists of two structural elements, the MWS (Main Web Server) and the WS (WorkStation). The MWS undertakes the management of the users and the available WSs. Each one of the multiple WSs is exclusively responsible for the conduction of the supported remote experiments. The communication between the MWS and the WSs is achieved through an internet accessible database. Therefore, the WSs can be installed in any geographic location allowing the development of federal RLs. However, the most important feature of the proposed architecture which contributes decisively to the sustainability of a RL, is the support of remote experiments designed and implemented by the users. In order to confirm the ARIAL, this Ph.D. dissertation also proposes a RL in digital signal processing with DSPs which is called R-DSP Lab (Remote Digital Signal Processors Laboratory). The R-DSP Lab provides the users with the ability either to perform one of the predefined remote experiments or to confirm the operation of a DSP application which is developed by them. In addition, the proposed RL allows the development of remote experiments by the users. In this case, the users implement offline both the desired DSP application and the GUI (Graphical User Interface) which undertakes the remote control of the above DSP application. During the conduction of the above remote experiments, the users are able to remote control the available laboratory instruments through a carefully designed web page. Subsequently, a RL in digital image processing with DSPs which is called R-DImPr Lab (Remote Digital Image Processing Laboratory), is also proposed. This RL allows the verification of a DSP application developed by the user utilizing the API (Application Program Interface) of R-DImPr Lab. The DSP application undertakes the digital process of images which are captured by the available image sensor. During the conduction of the remote experiment, the user through the web page of the proposed RL, selects the parameters of the image sensor and observes both the original and the processed image. In order to expand the features of the R-DImPr Lab, a digital image processing system based on DSPs was designed and developed. This system allows the users to perform remote experiments by controlling remotely both the DSP application and the position of the image sensor. The control of the image sensor’s position is achieved through a motion actuator which is based on two stepper motors and allows the rotation of the image sensor in two axes. In addition, this Ph.D. dissertation explores the possibility of the development of remote experiments in digital image processing with DSPs by the users utilizing the features of the R-DSP Lab. Finally, a RL in computer architecture which allows the users to program in assembly language one of the two available CPUs (Central Processing Units), is proposed. During the verification process, the implementation of the system which is based on the selected CPU, is loaded into the FPGA (Field Programmable Gate Array) of the available development platform. The users through the GUI of the proposed RL’s web page, are able to observe the micro-operations which take place in the selected CPU during the step by step program execution.

<p>The most important aspects of nuclear medicine imaging systems such as Positron Emission Tomography (PET) or Single Photon Emission Computed Tomography (SPECT) are the spatial resolution and the sensitivity (detector efficiency in combination with the geometric efficiency). Considerable efforts have been spent during the last two decades in improving the resolution and the efficiency by developing new detectors. Our proposed improvement technique is focused on the readout and electronics. Instead of using traditional pulse height analysis techniques we propose using free running digital sampling by replacing the analog readout and acquisition electronics with fully digital programmable systems.</p><p>This thesis describes a fully digital data acquisition system for KS/SU SPECT, new algorithms for high resolution timing for PET, and modular FPGA based decentralized data acquisition system with optimal timing and energy. The necessary signal processing algorithms for energy assessment and high resolution timing are developed and evaluated. The implementation of the algorithms in field programmable gate arrays (FPGAs) and digital signal processors (DSP) is also covered. Finally, modular decentralized digital data acquisition systems based on FPGAs and Ethernet are described.</p>

The most important aspects of nuclear medicine imaging systems such as Positron Emission Tomography (PET) or Single Photon Emission Computed Tomography (SPECT) are the spatial resolution and the sensitivity (detector efficiency in combination with the geometric efficiency). Considerable efforts have been spent during the last two decades in improving the resolution and the efficiency by developing new detectors. Our proposed improvement technique is focused on the readout and electronics. Instead of using traditional pulse height analysis techniques we propose using free running digital sampling by replacing the analog readout and acquisition electronics with fully digital programmable systems. This thesis describes a fully digital data acquisition system for KS/SU SPECT, new algorithms for high resolution timing for PET, and modular FPGA based decentralized data acquisition system with optimal timing and energy. The necessary signal processing algorithms for energy assessment and high resolution timing are developed and evaluated. The implementation of the algorithms in field programmable gate arrays (FPGAs) and digital signal processors (DSP) is also covered. Finally, modular decentralized digital data acquisition systems based on FPGAs and Ethernet are described.

<p>There is a lot of applications for DSPs (Digital Signal Processor) in the most rapidly growing areas in the industry right now as wireless communication along with audio and video products are getting more and more popular. In this report, a DSP, developed at the division of Computer Engineering at the University of Linköping, is optimized and verified.</p><p>Register Forwarding was implemented on a general architecture level to avoiddata hazards that may arise when implementing instruction pipelining in a processor.</p><p>The very common FFT algorithm is also optimized but on instruction setlevel. That means the algorithm is carefully analyzed to find operations that mayexecute in parallel and then create new instructions for these parallel operations.The optimization is concentrated on the butterfly operation as it is such a majorpart of the FFT computation. Comparing the accelerated butterfly with the unaccelerated gives an improvement of 30% in terms of clock cycles needed for thecomputation.</p><p>In the report there are also some discussions about the benefits and drawbacksof changing from a hardware to a software stack, mostly in terms of interrupts andthe return instruction.</p><p>Another important property of the processor is scalability. That is, it is possibleto attach extra peripherals to the core, which accelerates certain tasks. Aninterface towards these peripherals is developed along with two template designsthat may be used to develop other peripherals.</p><p>After all these modifications, a new test bench is developed to verify the functionality.</p>

Made available in DSpace on 2014-12-17T14:55:55Z (GMT). No. of bitstreams: 1 JoaoCSF_DISSERT.pdf: 4517412 bytes, checksum: 2112619de393ca975c806fa334e083ff (MD5) Previous issue date: 2011-12-19 / Coordena??o de Aperfei?oamento de Pessoal de N?vel Superior / Relevant researches have been growing on electric machine without mancal or bearing and that is generally named bearingless motor or specifically, mancal motor. In this paper it is made an introductory presentation about bearingless motor and its peripherical devices with focus on the design and implementation of sensors and interfaces needed to control rotor radial positioning and rotation of the machine. The signals from the machine are conditioned in analogic inputs of DSP TMS320F2812 and used in the control program. This work has a purpose to elaborate and build a system with sensors and interfaces suitable to the input and output of DSP TMS320F2812 to control a mancal motor, bearing in mind the modularity, simplicity of circuits, low number of power used, good noise imunity and good response frequency over 10 kHz. The system is tested at a modified ordinary induction motor of 3,7 kVA to be used with a bearingless motor with divided coil / Relevantes pesquisas v?m sendo desenvolvidas em m?quinas el?tricas sem mancais mec?nicos ou rolamentos e que s?o, genericamente, denominadas m?quinas sem mancais ou, em car?ter espec?fico, motor mancal. Neste trabalho faz-se uma abordagem introdut?ria sobre as m?quinas sem mancais e apresenta??o de seus dispositivos perif?ricos enfatizado o projeto e implementa??o de sensores e interfaces necess?rios ao controle de posicionamento radial do rotor e rota??o da m?quina. Os sinais oriundos da m?quina s?o condicionados ?s entradas anal?gicas do DSP TMS320F2812 e utilizados no programa de controle. Este trabalho tem por proposta elaborar e implementar um sistema envolvendo sensores e interfaces compat?veis as entradas e sa?das do DSP TMS320F2812, para controle de um motor mancal, tendo como foco a modularidade, simplicidade de circuitos, redu??o das fontes de alimenta??o, melhoria na imunidade a ru?dos e melhor resposta em frequ?ncia acima de 10 kHz. O sistema ? testado em um motor de indu??o de 3,7 kVA modificado para operar como uma m?quina sem mancais com bobinado dividido

There is a lot of applications for DSPs (Digital Signal Processor) in the most rapidly growing areas in the industry right now as wireless communication along with audio and video products are getting more and more popular. In this report, a DSP, developed at the division of Computer Engineering at the University of Linköping, is optimized and verified. Register Forwarding was implemented on a general architecture level to avoiddata hazards that may arise when implementing instruction pipelining in a processor. The very common FFT algorithm is also optimized but on instruction setlevel. That means the algorithm is carefully analyzed to find operations that mayexecute in parallel and then create new instructions for these parallel operations.The optimization is concentrated on the butterfly operation as it is such a majorpart of the FFT computation. Comparing the accelerated butterfly with the unaccelerated gives an improvement of 30% in terms of clock cycles needed for thecomputation. In the report there are also some discussions about the benefits and drawbacksof changing from a hardware to a software stack, mostly in terms of interrupts andthe return instruction. Another important property of the processor is scalability. That is, it is possibleto attach extra peripherals to the core, which accelerates certain tasks. Aninterface towards these peripherals is developed along with two template designsthat may be used to develop other peripherals. After all these modifications, a new test bench is developed to verify the functionality.

International Telemetering Conference Proceedings / October 21, 2002 / Town & Country Hotel and Conference Center, San Diego, California / Because modern data acquisition systems use digital backplanes, it is logical for more and more data processing to be done in each Data Acquisition Unit (DAU) or even in each module. The processing related to an analog acquisition module typically takes the form of digital signal conditioning for range adjust, linearization and filtering. Some of the advantages of this are discussed in this paper. The next stage is powerful processing boards within DAUs for data reduction and third-party algorithm development. Once data is being written to and from powerful processing modules an obvious next step is networking and decom-less access to data. This paper discusses some of the issues related to these types of processing.

Low frequency radio astronomy has entered a second golden age driven by the development of a new class of large-N interferometric arrays. The low frequency array (LOFAR) and a number of redshifted HI Epoch of Reionization (EoR) arrays are currently undergoing commission and regularly observing. Future arrays of unprecedented sensitivity and resolutions at low frequencies, such as the square kilometer array (SKA) and the hydrogen epoch of reionization array (HERA), are in development. The combination of advancements in specialized field programmable gate array (FPGA) hardware for signal processing, computing and graphics processing unit (GPU) resources, and new imaging and calibration algorithms has opened up the oft underused radio band below 300 MHz. These interferometric arrays require efficient implementation of digital signal processing (DSP) hardware to compute the baseline correlations. FPGA technology provides an optimal platform to develop new correlators. The significant growth in data rates from these systems requires automated software to reduce the correlations in real time before storing the data products to disk. Low frequency, widefield observations introduce a number of unique calibration and imaging challenges. The efficient implementation of FX correlators using FPGA hardware is presented. Two correlators have been developed, one for the 32 element BEST-2 array at Medicina Observatory and the other for the 96 element LOFAR station at Chilbolton Observatory. In addition, calibration and imaging software has been developed for each system which makes use of the radio interferometry measurement equation (RIME) to derive calibrations. A process for generating sky maps from widefield LOFAR station observations is presented. Shapelets, a method of modelling extended structures such as resolved sources and beam patterns has been adapted for radio astronomy use to further improve system calibration. Scaling of computing technology allows for the development of larger correlator systems, which in turn allows for improvements in sensitivity and resolution. This requires new calibration techniques which account for a broad range of systematic effects. And, a deep integration between DSP hardware and software data reduction into a single backend.