In this thesis, two different processor designs, LEON3 microcontroller and ADSP-218x digital signal processor, are integrated in an AMBA-based SoC platform. The SoC platform is based on the LEON3 AHB that includes a LEON3 microcontroller and other interfaces and debugging units. We add the ADSP-218x processor into the platform. The design of ADSP processor includes both the processor core design and the AMBA bus interface design. In addition, we extend the bit accuracy of the original 16-bit DSP to 32-bit and add the feature of single-instruction-multiple-data (SIMD) into the DSP core to improve the performance in digital signal processing applications. We also test several application examples executed on the two different processors and analyze their performance differences.

This thesis proposes an implementation of a DSP-Based single-phase small-scale photovoltaic energy conversion system. The conversion system converts dc power generated by photovoltaic cells into ac power. A digital signal processor and a combined circuit with push-pull and full-bridge architectures are used in this study to reduce the complexity of the circuit design. Several operation and protection functions, such as maximum power point tracking, over/under voltage protection, over current protection, over/under frequency protection and detection of islanding operation are considered in the design. The operation performance of the conversion system at different stages is analyzed. The proposed conversion system can supply the local loads and feed excess power to the utility network with unit power factor (grid-connection mode), or it can supply loads exclusively (stand-alone mode). The simulation and experimentation results are presented and discussed to show the performance of the photovoltaic system and verify the feasibility of the proposed energy conversion system.

International Telemetering Conference Proceedings / October 17-20, 1994 / Town & Country Hotel and Conference Center, San Diego, California / This paper discusses the use of DSP technology in the embedded real time ingest and pre-processing of weather satellite data. Specifically, case studies are presented in the use of Texas Instrument TMS 320 processors as front-end handlers of GOES MODE AAA and GOES GVAR data formats.

No description available.

This thesis discusses the implementation of a digital signal processor (DSP), including the DSP core and the peripheral interfaces. The DSP core includes three parallel computational units (arithmetic/logic unit, multiplier/accumulator, and barrel shifter), two independent data address generators, and a powerful program sequencer. The I/O designs provide two kinds of interfaces: serial ports and direct memory access (DMA) ports. The DMA contains two modes: full memory mode and host mode. To reduce power consumption in the instruction memory access, we add an instruction buffer for nested loops where the instructions in a loop are fetched only once and then put into the instruction buffer to be used in the subsequent iterations. The DSP implementation has passed the verification procedures both in the front-end synthesis by Synopsys Design Compiler and the back-end post-layout simulation by Nanosim. Furthermore, some benchmark DSP application programs such as FFT, FIR, and DCT are executed on the implemented DSP core.

We propose to design a DSP based image acquisition and pattern recognition system. This system which could mainly apply to do the vision guided automatic drill on the Flexible Printed Circuit Board (FPCB) includes three sub systems as ¡§Image acquisition system¡¨ , ¡§Pattern recognition system¡¨ and ¡§PCI communication system¡¨ . First , we obtain the FPCB image by the CCD camera , and do the pattern match for the drill goal on it . After computing , DSP transmits the goal coordinates to the computer user interface application . By the experiment result , we successfully make the whole system match the original purpose by using two image pre-process steps.

The purpose of this research is to develop a fixed-point arithmetic model based on a common general purpose Digital Signal Processor (DSP). A detailed non-linear model is developed to emulate the convergent (un-biased) rounding process performed by the Motorola DSP56002 fixed-point DSP. This model is incorporated into several different filter structures and compared to the linear stochastic simulation and the actual hardware implementation. It turns out that the convergent rounding operation has an insignificant effect on the overall roundoff noise power. The Direct Form, Section Optimal and MA Lattice forms are studied. F or these structures, Matlab routines are developed to automate the process of fixed-point scaling and DSP56002 code generation. Each structure's non-linear simulation is validated using two filter examples. The scaling and simulation routines allow the filter designer to investigate the finite word length performance of various structures, scaling norms, overflow safety factors, and word lengths to determine the best filter parameters prior to hardware implementation. / Master of Science

International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada / In this paper, a new concept in PCM telemetry encoding equipment is described. Existing "programmable" PCM encoders allow only simple changes in the functionality of the hardware, such as input gain, offset, and word formatting. More importantly, these encoders do not provide capability for "in-flight" processing of signals and in general have not taken advantage of existing hardware and software digital signal processing technology. In-flight processing of signals can provide a significant reduction in the required transmission bandwidth, allowing additional data that may not have otherwise been transmitted to be sent on the telemetry channel. A modular digital signal processor (DSP) based PCM encoder architecture is described that has a set of on-board processing algorithms configurable via a simple-to-use graphical user interface. Algorithms included are compression (lossy and lossless), Fourier transforms of various resolutions (typically followed by peak detection to provide a data rate reduction), extreme values (max, min, rms), time filtering, regression, trajectory prediction, and serial data stream processing. Custom algorithms can be developed and included as part of the suite of processing algorithms. The preprocessing algorithms exist as firmware on the DSPs and can accommodate as many different signals as the processing bandwidth of the DSP can handle. Typically one DSP can handle many input signals and different algorithms. The encoder is programmable via a standard RS-232 serial interface allowing the signal input configuration, telemetry frame layout, and on-board processing algorithms to be changed quickly.

One technique that is used to reduce the errors brought upon signals, when transmitted over noisy channels, is error control coding. One type of such coding, which has a good performance, is turbo coding. In some of the TMS320C64xTM digital signal processors there is a built in coprocessor that performs turbo decoding. This thesis is performed on the account of Communication Developments, within Saab AB and presents an evaluation of this coprocessor. The evaluation deals with both the memory consumption as well as the data rate. The result is also compared to an implementation of turbo coding that does not use the coprocessor. / En teknik som används för att minska de fel som en signal utsätts för vid transmission över en brusig kanal är felrättande kodning. Ett exempel på sådan kodning som ger ett mycket bra resultat är turbokodning. I några digitalsignalprocessorer, av sorten TMS320C64xTM, finns en inbyggd coprocessor som utför turboavkodning. Denna uppsats är utförd åt Communication Development inom Saab AB och presenterar en utvärdering av denna coprocessor. Utvärderingen avser såväl minnesförbrukning som datatakt och innehåller även en jämförelse med en implementering av turbokodning utan att använda coprocessorn.

The switched reluctance motor has the advantages of the low production cost, high operating efficiency, high stability, and high start torque. It can deliver a wide speed range, and therefore make it very attractive to the engineers and researchers. The double salient structure of SRM result in a non-linear stator inductance, so the output reluctance torque has a highly non-linear behavior. A digital signal processor based drive system for SRM is developed and implemented in this thesis using the TI TMS320F240 DSP system which is with universal peripheral interface circuits. The built-in pulse width modulation(PWM) module of the DSP system can auto-generate PWM output signal by setting the relative registers to simplify the hardware design. This research built a complete drive system for SRM, both the closed-loop velocity controller and current compensator were designed according to the proportional-integral(PI) control mechanism, and all schemes were coded in the DSP program. Simulation and experiment results demonstrate that the proposed drive system makes reluctance torque output very smoothly with a preferable velocity response.