<p>Ова докторска теза описује и анализира приступ развоју Це компајлера за<br />наменске процесоре. Такав компајлер захтева имплементацију посебних<br />техника и алгоритама, претежно специфичних за нерегуларне процесорске<br />архитектуре, да би генерисао ефикасан код, и при том је потребно да<br />испуњава индустријске стандарде по питању робустности, разумљивости<br />кода, могућности одржавања и проширивости. У ту сврху је предложена<br />нова компајлерска инфраструктура над којом је имплементиран компајлер<br />за Cirrus Coyote 32 ДСП. Квалитет генерисаног кода поређен је са<br />квалитетом кода генерисног од стране већ постојећег компајлера за тај<br />процесор. Уједно, одређени елементи организације компајлера су<br />упоређени са популарним компајлерима отвореног кода GCC и LLVM.</p> / <p>Ova doktorska teza opisuje i analizira pristup razvoju Ce kompajlera za<br />namenske procesore. Takav kompajler zahteva implementaciju posebnih<br />tehnika i algoritama, pretežno specifičnih za neregularne procesorske<br />arhitekture, da bi generisao efikasan kod, i pri tom je potrebno da<br />ispunjava industrijske standarde po pitanju robustnosti, razumljivosti<br />koda, mogućnosti održavanja i proširivosti. U tu svrhu je predložena<br />nova kompajlerska infrastruktura nad kojom je implementiran kompajler<br />za Cirrus Coyote 32 DSP. Kvalitet generisanog koda poređen je sa<br />kvalitetom koda generisnog od strane već postojećeg kompajlera za taj<br />procesor. Ujedno, određeni elementi organizacije kompajlera su<br />upoređeni sa popularnim kompajlerima otvorenog koda GCC i LLVM.</p> / <p>This PhD thesis describes and analyses an approach to development of C<br />language compiler for embedded processors. That kind of compiler requires<br />implementation of special techniques and algorithms, mostly specific for<br />irregular processor architectures, in order to be able to generate efficient<br />code, whereas still meeting industrial strength standard by beeing robust,<br />understandable, maintainable, and extensible. For this purpose the new<br />compiler insfrastructure is proposed and on top of it a compiler for Cirrus<br />Logic Coyote 32 DSP is built. Quality of the code generated by that compiler<br />is compared with code generated by the previous compiler for the same<br />processor architecture. Some elements of the compiler design are also<br />compared to popular open source compilers GCC and LLVM.</p>

The first version of the Senior processor was created as part of a thesis projectin 2007. This processor was completed and used for educational purposes atLinköpings University. In 2008 several parts of the processor were optimized andthe processor expanded with additional functionality as part of another thesisproject. In 2009 an EU funded project called MULTI-BASE started, in which theComputer Division at the Department of Electrical Engineering participated in.For their part of the MULTI-BASE project, the Senior processor was selected tobe used. After continuous revision and development, this processor was sent formanufacturing. The assignment of this thesis project was to test and verify the different func-tions implemted in the Senior processor. To do this a PCB was developed fortesting the Senior processor together with a Virtex-4 FPGA. Extensive testingwas done on the most important functions of the Senior processor. These testsshowed that the manufactured Senior processor works as designed and that it alonecan perform larger calculations and use external hardware accelerators with thehelp of its various interfaces. / Den första versionen av Senior processorn skapades som en del i ett examensarbe-te under 2007, denna processor färdigställdes och användes i utbildningssyfte påLinköping Universitet. 2008 optimerades flera delar av processorn och utökadesmed extra funktionalitet som del av ytterligare ett examensarbete. 2009 startadeett EU finansierat projekt vid namn MULTI-BASE, som ISYs Datortekniks avdel-ning deltar i. Till deras del av MULTI-BASE projektet valdes Senior processorn attanvändas, efter ytterligare utveckling skickades denna processor för tillverkning. Detta examensarbete hade i uppgift att testa och verifiera de olika funktionernasom Senior processorn har implementerats med. För att göra detta tillverkades ettkretskort som ska användas för att testa Senior processorn tillsammans med enVirtex-4 FPGA. Utförliga tester gjordes på de viktigaste funktionerna hos Seniorprocessorn, dessa tester visade att den tillverkade Senior processorn fungerar somplanerat. Den kan på egen hand utföra större beräkningar och använda sig avexterna hårdvare acceleratorer med hjälp av sina olika gränssnitt.

The McTronX research group at the North-West University is currently researching self-sensing techniques for Active Magnetic Bearings (AMB). The research is part of an ongoing effort to expand the knowledge base on AMBs in the School of Electrical, Electronic and Computer Engineering to support industries that make use of the technology. The aim of this project is to develop an integrated co-processor based power electronic drive with the emphasis placed on the ability of the co-processor to execute AMB self-sensing algorithms. The two primary techniques for implementing self-sensing in AMBs are state estimation and modulation. This research focuses on hardware development to facilitate the implementation of the modulation method. Self-sensing algorithms require concurrent processing power and speed that are well suited to an architecture that combines a digital signal processor (DSP) and a field programmable gate array (FPGA). A comprehensive review of various power amplifier topologies shows that the pulse width modulation (PWM) switching amplifier is best suited for controlling the voltage and current required to drive the AMB coils. Combining DSPs and power electronics to form an integrated co-processor based power electronic drive requires detail attention to aspects of PCB design, including signal integrity and grounding. A conceptual design is conducted and forms part of the process of compiling a subsystem development specification for the integrated drive, in conjunction with the McTronX Research Group. Component selection criteria, trade-off studies and various circuit simulations serve as the basis for this essential phase of the project. The conceptual design and development specification determines the architecture, functionality and interfaces of the integrated drive. Conceptual designs for the power amplifier, digital controller, electronic supply and mechanical layout of the integrated drive is provided. A detail design is performed for the power amplifier, digital controller and electronic supply. Issues such as component selection, power supply requirements, thermal design, interfacing of the various circuit elements and PCB design are covered in detail. The output of the detail design is a complete set of circuit diagrams for the integrated controller. The integrated drive is interfaced with existing AMB hardware and facilitates the successful implementation of two self-sensing techniques. The hardware performance of the integrated coprocessor based power electronic drive is evaluated by means of measurements taken from this experimental self-sensing setup. The co-processor performance is evaluated in terms of resource usage and execution time and performs satisfactorily in this regard. The integrated co-processor based power electronic drive provided sufficient resources, processing speed and flexibility to accommodate a variety of self-sensing algorithms thus contributing to the research currently underway in the field of AMBs by the McTronX research group at the North-West University. / Thesis (M.Ing. (Electrical Engineering))--North-West University, Potchefstroom Campus, 2009.

The McTronX research group at the North-West University is currently researching self-sensing techniques for Active Magnetic Bearings (AMB). The research is part of an ongoing effort to expand the knowledge base on AMBs in the School of Electrical, Electronic and Computer Engineering to support industries that make use of the technology. The aim of this project is to develop an integrated co-processor based power electronic drive with the emphasis placed on the ability of the co-processor to execute AMB self-sensing algorithms. The two primary techniques for implementing self-sensing in AMBs are state estimation and modulation. This research focuses on hardware development to facilitate the implementation of the modulation method. Self-sensing algorithms require concurrent processing power and speed that are well suited to an architecture that combines a digital signal processor (DSP) and a field programmable gate array (FPGA). A comprehensive review of various power amplifier topologies shows that the pulse width modulation (PWM) switching amplifier is best suited for controlling the voltage and current required to drive the AMB coils. Combining DSPs and power electronics to form an integrated co-processor based power electronic drive requires detail attention to aspects of PCB design, including signal integrity and grounding. A conceptual design is conducted and forms part of the process of compiling a subsystem development specification for the integrated drive, in conjunction with the McTronX Research Group. Component selection criteria, trade-off studies and various circuit simulations serve as the basis for this essential phase of the project. The conceptual design and development specification determines the architecture, functionality and interfaces of the integrated drive. Conceptual designs for the power amplifier, digital controller, electronic supply and mechanical layout of the integrated drive is provided. A detail design is performed for the power amplifier, digital controller and electronic supply. Issues such as component selection, power supply requirements, thermal design, interfacing of the various circuit elements and PCB design are covered in detail. The output of the detail design is a complete set of circuit diagrams for the integrated controller. The integrated drive is interfaced with existing AMB hardware and facilitates the successful implementation of two self-sensing techniques. The hardware performance of the integrated coprocessor based power electronic drive is evaluated by means of measurements taken from this experimental self-sensing setup. The co-processor performance is evaluated in terms of resource usage and execution time and performs satisfactorily in this regard. The integrated co-processor based power electronic drive provided sufficient resources, processing speed and flexibility to accommodate a variety of self-sensing algorithms thus contributing to the research currently underway in the field of AMBs by the McTronX research group at the North-West University. / Thesis (M.Ing. (Electrical Engineering))--North-West University, Potchefstroom Campus, 2009.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2011. / ENGLISH ABSTRACT: The digital control of UPS systems has been difficult in the past due to a lack of DSP technology. It was for this reason not possible to establishing the necessary control to regulate the voltages and currents of the UPS systems. Recent advances in DSP technology have however provided the means of establishing central control of the UPS system as well as incorporating more complex closed-loop control algorithms by utilising a single floating-point DSP. Closed-loop control strategies are investigated and the central control of a line-interactive UPS is established in this study. Both the status of the physical system as well as various system parameters are controlled. The system both regulates and charges the storage batteries when the main utility supply is maintained. In the event that the utility fails, the converter instantaneously changes power flow towards the load with the aim of maintaining an uninterrupted voltage supply. Several closed-loop deadbeat based control strategies are investigated for the regulation of the inductor current. A solution for the regulation of the DC-link is also developed and implemented. Furthermore, an intensive study is done on the regulation of the voltage supplied to the load in the event that the utility supply fails. The investigation is initially approached by considering classical control theory. Although these control strategies provided sufficient results, a predictive strategy that is based on the physical conditions of the switching converter is finally investigated to establish closed loop control of the output voltage. This resulted in a high-bandwidth voltage controller capable of maintaining control under a wide-array of load conditions. / AFRIKAANSE OPSOMMING: Die digitale beheer van UPS stelsels was moeilik in the verlede as gevolg van 'n gebrek aan DSP tegnologie. Dit was vir hierdie rede nie moontlik om beheer te kon bewerkstelling ten einde die spannings and strome in the UPS stelsels te kon reguleer nie. Onlangse vordering in DSP tegnologie het egter dit moontlik gemaak om sentrale beheer van die UPS stelsel te bewerkstellig sowel as om meer komplekse geslote lus beheer algoritmes te inkorporeer met behulp van 'n enkele DSP. Geslote lus beheer strategiëe word ondersoek en die sentrale beheer van die line-interaktiewe UPS word bewerkstellig in hierdie studie. Beide die huidige toestand van die fisiese stelsel sowel as die verskeie parameters word beheer. Die stelsel beide laai en reguleer die batterye terwyl die hooftoevoer onderhou word. In die geval dat die hooftoevoer faal, word die omsetter se rigting van drywingsvloei verander om die las te voorsien van 'n ononderbroke spannings toevoer. Verskeie geslote-lus “deadbeat” beheer strategiëe word ondersoek vir die regulasie van die induktor stroom. 'n Oplossing vir die regulasie van die GS-koppervlak word ook ontwikkel en geïmplementeer. Verder word 'n intensiewe studie gedoen op regulasie van die spanning wat aan die las gevoer word in die geval dat die hooftoevoer faal. Hierdie ondersoek word aanvanklik benader deur klassieke beheer teorie te bestudeer. Alhoewel hierdie beheer strategiëe voldoene resultate gebied het, was 'n voorspel beheerstrategie gebaseer op die fisiese toestand van die omsetter finaal ondersoek. Die resultaat is 'n hoë-bandwydte spannings beheerder wat daartoe instaat is om beheer te handhaaf onder 'n verskeidenheid van lastoestande.

Orientador: Ricardo Tokio Higuti / Banca: Alexandre César Rodrigues da Silva / Banca: Flávio Buiochi / Resumo: A estimação do tempo de atraso entre dois sinais de ultra-som é uma tarefa muito comum e importante em diversas aplicações, como em sistemas de posicionamento para medição de distâncias, medidores de espessura em ensaios não-destrutivos, células de medição de propriedades de materiais, entre outros. Em algumas aplicações há necessidade de elevada acurácia e precisão na determinação do tempo de atraso, que dependem de diversos parâmetros do transdutor, de sua excitação e do meio em que a onda se propaga, além do método de estimação e representação numérica. Neste trabalho são avaliados três estimadores de tempo de atraso, com implementações em ponto-fixo e ponto-flutuante: correlação cruzada com interpolação parabólica, transformada de Hilbert da correlação e envoltória do sinal analítico. Os estimadores são avaliados em MATLAB, em ponto-flutuante, com sinais sintetizados e com sinais reais obtidos em laboratório, e em ponto-fixo, usando um processador digital de sinais TMS320VC5416, da Texas Instruments. São explorados parâmetros como freqüência central do transdutor, freqüência de amostragem, largura de banda, relação sinal-ruído e atenuação do meio. O desempenho dos métodos é comparado por meio dos erros médios e desvios-padrão das medidas / Abstract: Time-delay estimation between two ultrasonic signals is a very common and important task in several applications, such as distance measurement in positioning systems, thickness measurement in nondestructive testing, measurement cells of materials properties, among others. Some applications require high accuracy and precision on the determination of the time-delay, which depend on several transducer parameters, excitation and medium of propagation, as well as the estimation method and numerical representation. In this work, three time-delay estimators are evaluated, with fixed- and floating-point implementations: cross-correlation with parabolic interpolation, Hilbert transform of correlation and analytic signal envelope. The estimators are evaluated in MATLAB with floating-point representation, using synthesized signals and real signals acquired in laboratory, and in fixed-point using a Texas Instruments TMS320VC5416 digital signal processor. Parameters as transducer central frequency, sampling frequency, bandwidth, signal-to-noise ratio and medium attenuation are considered. The performances of the methods are compared by means of errors (or bias) and standard deviations / Mestre

Abstract The multiple-input multiple-output (MIMO) technique combined with an orthogonal frequency division multiplexing (MIMO--OFDM) has been introduced as a promising approach for the ever increasing capacity and quality of service (QoS) requirements for wireless communication systems. An efficient radio spectrum utilization expects a flexible transceiver solution, which has been the reason for the development of the software defined radio (SDR) technologies which in their turn are expected to enable the creation of cognitive radios. As a result, any radio solution could be invoked on demand on any platform. In this thesis work, we have studied detector algorithms and programmable processor architectures in order to find practical solutions for the future wireless systems. A programmable receiver can reduce the energy dissipation of the receiver by changing the detection algorithm based on the current channel realizations. To provide a realistic aspect to the implementations in different channel realizations, we present a wide state-of-the-art detector comparison. In addition, we present an extensive number arithmetic and word length study in order to evaluate realistic hardware complexity and energy dissipations of the implementations. The study includes a comprehensive design chain from the algorithm development to the actual processor design and finally programming software for the platforms. We evaluate single and multi-core processor implementations by comparing the achieved results to the Long Term Evolution (LTE) performance requirements. We implement detectors on digital signal processors (DSPs), graphics processing unit (GPU) and transport triggered architecture (TTA). The implementation results are compared in throughput, silicon area and energy efficiency. Finally, we discuss the advantages and disadvantages of the architectures and the implementation effort. / Tiivistelmä Usean antennin tekniikka yhdistettynä ortogonaaliseen taajuusvaihtelumodulointiin lähetin-vastaanotimessa on esitetty eräänä lupaavana ratkaisuna jatkuvasti kasvaviin kapasiteetti- ja palvelunlaatuvaatimuksiin langattomissa tietoliikennejärjestelmissä. Tehokas radiospektrin käyttö edellyttää joustavaa lähetin-vastaanotinratkaisua, mikä on ollut syynä ohjelmistoradioteknologioiden kehitykselle. Ohjelmistoradioiden kehityksen on puolestaan odotettu mahdollistavan kognitiiviradioiden syntymisen. Tuloksena, mikä tahansa radiosovellus voitaisiin herättää tarpeen mukaan millä tahansa ohjelmoitavalla sovellusalustalla. Tässä väitöskirjatyössä tutkitaan ilmaisinalgoritmeja sekä ohjelmoitavia prosessoriarkkitehtuureja tarkoituksena löytää käytännöllisiä ratkaisuja tulevaisuuden langattomiin järjestelmiin. Ohjelmoitavalla vastaanottimella voidaan vähentää vastaanottimen energiankulutusta vaihtamalla ilmaisinalgoritmeja vallitsevan kanavatilan mukaan. Työssä esitellään laaja, viimeisintä tutkimusta edustava ilmaisinalgoritmivertailu, joka antaa realistisen näkökannan toteutuksiin erilaisissa kanavatiloissa. Lisäksi työssä esitellään numeroaritmetiikka- ja sananpituustutkimus, jonka tarkoituksena on arvioida toteutusten realistista kovokompleksisuutta sekä energiankulutusta. Tutkimus sisältää kattavan suunnitteluketjun algoritmikehityksestä todelliseen prosessorisuunnitteluun ja lopulta algoritmin ohjelmointiin tietylle sovellusalustalle. Väitöskirjatyössä arvioidaan yksi- ja moniytimisiä prosessoritoteutuksia vertaamalla saavutettuja tuloksia Long Term Evolution -standardin suorituskykyvaatimuksiin. Ilmaisimia toteutetaan digitaalisilla signaaliprosessoreilla, grafiikkaprosessorilla sekä siirtoliipaisuarkkitehtuurilla. Toteutustuloksia vertaillaan laskentatehona, pinta-alana sekä energiatehokkuutena. Lopuksi käsitellään arkkitehtuurien hyviä ja huonoja puolia sekä suunnittelun työläyttä.

During the past two decades, many researchers have developed methods for the detection of structural defects at the early stages to operate the aerospace vehicles safely and to reduce the operating costs. The Surface Response to Excitation (SuRE) method is one of these approaches developed at FIU to reduce the cost and size of the equipment. The SuRE method excites the surface at a series of frequencies and monitors the propagation characteristics of the generated waves. The amplitude of the waves reaching to any point on the surface varies with frequency; however, it remains consistent as long as the integrity and strain distribution on the part is consistent. These spectral characteristics change when cracks develop or the strain distribution changes. The SHM methods may be used for many applications, from the detection of loose screws to the monitoring of manufacturing operations. A scanning laser vibrometer was used in this study to investigate the characteristics of the spectral changes at different points on the parts. The study started with detecting a load on a plate and estimating its location. The modifications on the part with manufacturing operations were detected and the Part-Based Manufacturing Process Performance Monitoring (PbPPM) method was developed. Hardware was prepared to demonstrate the feasibility of the proposed methods in real time. Using low-cost piezoelectric elements and the non-contact scanning laser vibrometer successfully, the data was collected for the SuRE and PbPPM methods. Locational force, loose bolts and material loss could be easily detected by comparing the spectral characteristics of the arriving waves. On-line methods used fast computational methods for estimating the spectrum and detecting the changing operational conditions from sum of the squares of the variations. Neural networks classified the spectrums when the desktop – DSP combination was used. The results demonstrated the feasibility of the SuRE and PbPPM methods.

During the past two decades, many researchers have developed methods for the detection of structural defects at the early stages to operate the aerospace vehicles safely and to reduce the operating costs. The Surface Response to Excitation (SuRE) method is one of these approaches developed at FIU to reduce the cost and size of the equipment. The SuRE method excites the surface at a series of frequencies and monitors the propagation characteristics of the generated waves. The amplitude of the waves reaching to any point on the surface varies with frequency; however, it remains consistent as long as the integrity and strain distribution on the part is consistent. These spectral characteristics change when cracks develop or the strain distribution changes. The SHM methods may be used for many applications, from the detection of loose screws to the monitoring of manufacturing operations. A scanning laser vibrometer was used in this study to investigate the characteristics of the spectral changes at different points on the parts. The study started with detecting a load on a plate and estimating its location. The modifications on the part with manufacturing operations were detected and the Part-Based Manufacturing Process Performance Monitoring (PbPPM) method was developed. Hardware was prepared to demonstrate the feasibility of the proposed methods in real time. Using low-cost piezoelectric elements and the non-contact scanning laser vibrometer successfully, the data was collected for the SuRE and PbPPM methods. Locational force, loose bolts and material loss could be easily detected by comparing the spectral characteristics of the arriving waves. On-line methods used fast computational methods for estimating the spectrum and detecting the changing operational conditions from sum of the squares of the variations. Neural networks classified the spectrums when the desktop – DSP combination was used. The results demonstrated the feasibility of the SuRE and PbPPM methods.

This work is aimed on design of a device for testing of fire detectors and various components of fire detection system, communicating with the fire panel over a fire bus or a loop. The device generates voltages, supplying the detectors, as well as communicating over the bus generating communication waveforms and performing detection of responses measuring voltage and current on the connection. The loop signal is processed by the developed unit and data or result sent to a PC utilizing USB or RS232 connection. All the parts of the equipment are galvanically isolated to the loop circuit.