Recently, smart dust or wireless sensor networks are gaining more attention.These autonomous, ultra-low power sensor-based electronic devices sense and process burst-type environmental variations and pass the data from one node (mote) to another in an ad-hoc network. Subsystems for smart dust are typically the analog interface (AI), analog-to-digital converter (ADC), digital signal processor (DSP), digital-to-analog converter (DAC), power management, and transceiver for communication. This thesis project describes an event-driven (ED) digital signal processing system (ADC, DSP and DAC) operating in continuous-time (CT) with smart dust as the target application. The benefits of the CT system compared to its conventional counterpart are lower in-band quantization noise and no requirement of a clock generator and anti-aliasing filter, which makes it suitable for processing burst-type data signals. A clockless EDADC system based on a CT delta modulation (DM) technique is presented. The ADC output is digital data, continuous in time, known as “data token”. The ADC employs an unbuffered, area efficient, segmented resistor-string (R-string) feedback DAC. A study of different segmented R-string DAC architectures is presented. A comparison in component reduction with prior art shows nearly 87.5% reduction of resistors and switches in the DAC and the D flip-flops in the bidirectional shift registers for an 8-bit ADC, utilizing the proposed segmented DAC architecture. The obtained SNDR for the 3-bit, 4-bit and 8-bit ADC system is 22.696 dB, 30.435 dB and 55.73 dB, respectively, with the band of interest as 220.5 kHz. The CTDSP operates asynchronously and process the data token obtained from the EDADC. A clockless transversal direct-form finite impulse response (FIR) low-pass filter (LPF) is designed. Systematic top-down test-driven methodology is employed through out the project. Initially, MATLAB models are used to compare the CT systems with the sampled systems. The complete CTDSP system is implemented in Cadence design environment. The thesis has resulted in two conference contributions. One for the 20th European Conference on Circuit Theory and Design, ECCTD’11 and the other for the 19th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC’11. We obtained the second-best student paper award at the ECCTD.

Στην παρούσα Διπλωματική Εργασία μελετάται η δομή και τα χαρακτηριστικά ενός νέου μετατροπέα ψηφιακού σήματος σε αναλογικό (Digital to Analog Converter DAC). Η δομή του DAC βασίζεται στη γνωστή δομή του συμβατικού R2R Ladder και θα μπορούσε να θεωρηθεί σαν μία δισδιάστατη ανάπτυξη του Ladder. Αυτό σημαίνει ότι η νέα μορφή του DAC χρησιμοποιεί σαφώς περισσότερες αντιστάσεις από τον συμβατικό Ladder, όμως δίνεται η δυνατότητα της ρύθμισης του ρεύματος εξόδου του κάθε κλάδου. Αυτό έχει ως συνέπεια τη δραματική βελτίωση της γραμμικότητας του DAC. Επιπλέον στην Εργασία αυτή μελετήθηκαν με χρήση της θεωρίας των πιθανοτήτων τα χαρακτηριστικά του απλού Ladder και χρησιμοποιήθηκαν για την εξαγωγή συμπερασμάτων που αφορούν στη γραμμικότητα της νέας δομής Ladder. Τα θεωρητικά αποτελέσματα επιβεβαιώθηκαν με εξομοιώσεις. Τέλος, μία σχεδίαση σε φυσικό επίπεδο με την χρήση μόνο MOSFETS και CMOS τεχνολογίας (χωρίς την χρήση αντιστάσεων) σχεδιάσθηκε και εξομοιώθηκε στο Cadence ένας Ladder της νέας δομής. / This Diploma Thesis studies on a new Digital to Analog Converter (DAC) structure developed in the Applied Electronics Laboratory of the University of Patras. The new DAC structure is based on the simple R2R ladder combining several of them in a 2-dimentional grid. As result a high linearity DAC is derived after a simple calibration procedure. The Diploma Thesis presents results on probability of the simple R2R Ladder, employs these results so as to forecast the linearity of the 2-dimentional Ladder, whereas confirms theoretical results with simulations. Finally, a DAC based on the 2-dimentional topology has been designed and simulated using Cadence, in the framework of this Diploma Thesis.

Une nouvelle méthode de test pour les convertisseurs ADC et DAC embarqués dans un système complexe a été développée en prenant en compte les nouvelles contraintes affectant le test. Ces contraintes, dues aux tendances de design de systèmes, sont un nombre réduit de point d'accès aux entrées/sorties des blocs analogiques du système et une augmentation galopante du nombre et des performances des convertisseurs intégrés. La méthode proposée consiste à connecter les convertisseurs DAC et ADC dans le domaine analogique pour n'avoir besoin que d'instruments de test numériques pour générer et capturer les signaux de test. Un algorithme de traitement du signal a été développé pour discriminer les erreurs des DACs et ADCs. Cet algorithme a été validé par simulation et par expérimentation sur des produits commercialisés par NXP. La dernière partie de la thèse a consisté à développer de nouvelles applications pour l'algorithme.

Silicon carbide (SiC) integrated circuits (ICs) can enable the emergence of robust and reliable systems, including data acquisition and on-site control for extreme environments with high temperature and high radiation such as deep earth drilling, space and aviation, electric and hybrid vehicles, and combustion engines. In particular, SiC ICs provide significant benefit by reducing power dissipation and leakage current at temperatures above 300 °C compared to the Si counterpart. In fact, Si-based ICs have a limited maximum operating temperature which is around 300 °C for silicon on insulator (SOI). Owing to its superior material properties such as wide bandgap, three times larger than Silicon, and low intrinsic carrier concentration, SiC is an excellent candidate for high-temperature applications. In this thesis, analog and mixed-signal circuits have been implemented using SiC bipolar technology, including bandgap references, amplifiers, a master-slave comparator, an 8-bit R-2R ladder-based digital-to-analog converter (DAC), a 4-bit flash analog-to-digital converter (ADC), and a 10-bit successive-approximation-register (SAR) ADC. Spice models were developed at binned temperature points from room temperature to 500 °C, to simulate and predict the circuits’ behavior with temperature variation. The high-temperature performance of the fabricated chips has been investigated and verified over a wide temperature range from 25 °C to 500 °C. A stable gain of 39 dB was measured in the temperature range from 25 °C up to 500 °C for the inverting operational amplifier with ideal closed-loop gain of 40 dB. Although the circuit design in an immature SiC bipolar technology is challenging due to the low current gain of the transistors and lack of complete AC models, various circuit techniques have been applied to mitigate these problems. This thesis details the challenges faced and methods employed for device modeling, integrated circuit design, layout implementation and finally performance verification using on-wafer characterization of the fabricated SiC ICs over a wide temperature range. / <p>QC 20170905</p>