In this research, a time-based oversampling delta-sigma (ΔΣ) ADC architecture is introduced. This system uses time, rather than voltage or current, as the analog variable for its quantizer, and the noise shaping process is realized by modulating the width of a variable-width digital “pulse.” The ΔΣ loop integrator, the quantizer and digital-to-analog converter (DAC) are all time-based circuits and are implemented using digital gates only. Hence, no amplifier or voltage-based circuit is required. The proposed architecture not only offers a viable for nano-scale ‘digital’ IC technologies, but also enables improved circuit performance compared to the state-of-the-art. This is in contrast to conventional voltage-based analog circuit design, whose performance decreases with scaling due to increasingly higher voltage uncertainty due to supply voltage. The proposed architecture allows all digital implementation after the Voltage to Time Converter (VTC) and merged multi-bit quantizer/DAC blocks by taking advantage of delay lines reusable in both quantization and DAC operation. The novelty of this architecture is digital pulse width processing to implement the ΔΣ modulation. It is realized with small area and potentially can take advantage from the process scaling. A 3-bit prototype of this ADC in 0.18 μm CMOS process is implemented, tested, and presented. With an OSR of 36 and a bandwidth of 2 MHz, it achieves a SNDR of 34.6 dB while consuming 1.5 mA from a 1.8 V supply. The core occupies an area of 0.0275 mm² (110μm × 250μm = 0.0275 mm²). The second generation of the architecture was fabricated in IBM 45 nm SOI process. The oversampling frequency of this system is 705 MHz and oversampling ratio of 64. The expected performance is 7-bit effective resolution for a 5.5 MHz bandwidth while consuming 8mW of power and occupying a core area of less than 0.02 mm² (160μm × 120μm = 0.0192 mm²). / text

This thesis presents time difference (TD) circuits that are important for measuring fluorescence lifetime, building LIDAR systems, and optimizing digital systems. The contribution of this thesis is to present a systematic organization of TD circuits and to present novel designs for digital-to-time conversion (DTC) and time-to-digital conversion (TDC). Four basic time difference circuits are presented: TD adder, arbiter, time-difference MUX, and time-difference memory. Specifications, symbols, and multiple circuit implementations are presented for each block. Then the basic blocks are combined to form two compound blocks: DTC and TDC. Novel designs are presented for both blocks along with detailed simulation results. The DTC was fabricated in TSMC’s 0.35um high-voltage process. A printed circuit board was designed to interface the DTC chip to a computer and test instruments. The DTC demonstrated 80ps resolution.