In recent years there has been increased interest in the development of sensorless switched reluctance machine drives. The proper operation of a switched reluctance machine (SRM) requires knowledge of the position of the rotor of the machine. The inclusion of a physical position sensor compromises the inherent robustness of this type of machine. Thus, there has been a need to develop techniques to estimate the position of the rotor in SRM drives. Switched reluctance machines are able to operate over a large range in speed. A fully loaded SRM is typically designed to saturate the ferromagnetic material that comprises the stator and rotor of the machine whereas a lightly loaded machine does not. Therefore, the model of the machine should be able to handle both a large range in frequency and input excitation levels of the magnetic material in the machine. The development of a new dynamic circuit-based ferromagnetic model is described in this thesis. The investigation of the behaviour of 24 gauge M19 silicon steel led to the conclusion that, for this material, a circuit model that has static parameters is unable to accurately reproduce the behaviour of the actual material over a large range of input frequencies and excitation levels without resorting to retuning the parameters of the model. This thesis provides two new mechanisms that dynamically adjust the resistance values of the flux tubes of the model. Comparisons using a normalized vertical least-squares metric between the newly proposed dynamic model and a model that has static resistance values clearly show the improvement that is gained by using these mechanisms. A practical implementation of the new model is also given. Timing using a general purpose CPU shows that this implementation of the model will most likely be able to be used as part of a multi-phase lumped parameter model for a SRM in realtime.

In recent years there has been increased interest in the development of sensorless switched reluctance machine drives. The proper operation of a switched reluctance machine (SRM) requires knowledge of the position of the rotor of the machine. The inclusion of a physical position sensor compromises the inherent robustness of this type of machine. Thus, there has been a need to develop techniques to estimate the position of the rotor in SRM drives. Switched reluctance machines are able to operate over a large range in speed. A fully loaded SRM is typically designed to saturate the ferromagnetic material that comprises the stator and rotor of the machine whereas a lightly loaded machine does not. Therefore, the model of the machine should be able to handle both a large range in frequency and input excitation levels of the magnetic material in the machine. The development of a new dynamic circuit-based ferromagnetic model is described in this thesis. The investigation of the behaviour of 24 gauge M19 silicon steel led to the conclusion that, for this material, a circuit model that has static parameters is unable to accurately reproduce the behaviour of the actual material over a large range of input frequencies and excitation levels without resorting to retuning the parameters of the model. This thesis provides two new mechanisms that dynamically adjust the resistance values of the flux tubes of the model. Comparisons using a normalized vertical least-squares metric between the newly proposed dynamic model and a model that has static resistance values clearly show the improvement that is gained by using these mechanisms. A practical implementation of the new model is also given. Timing using a general purpose CPU shows that this implementation of the model will most likely be able to be used as part of a multi-phase lumped parameter model for a SRM in realtime.

In recent years there has been increased interest in the development of sensorless switched reluctance machine drives. The proper operation of a switched reluctance machine (SRM) requires knowledge of the position of the rotor of the machine. The inclusion of a physical position sensor compromises the inherent robustness of this type of machine. Thus, there has been a need to develop techniques to estimate the position of the rotor in SRM drives. Switched reluctance machines are able to operate over a large range in speed. A fully loaded SRM is typically designed to saturate the ferromagnetic material that comprises the stator and rotor of the machine whereas a lightly loaded machine does not. Therefore, the model of the machine should be able to handle both a large range in frequency and input excitation levels of the magnetic material in the machine. The development of a new dynamic circuit-based ferromagnetic model is described in this thesis. The investigation of the behaviour of 24 gauge M19 silicon steel led to the conclusion that, for this material, a circuit model that has static parameters is unable to accurately reproduce the behaviour of the actual material over a large range of input frequencies and excitation levels without resorting to retuning the parameters of the model. This thesis provides two new mechanisms that dynamically adjust the resistance values of the flux tubes of the model. Comparisons using a normalized vertical least-squares metric between the newly proposed dynamic model and a model that has static resistance values clearly show the improvement that is gained by using these mechanisms. A practical implementation of the new model is also given. Timing using a general purpose CPU shows that this implementation of the model will most likely be able to be used as part of a multi-phase lumped parameter model for a SRM in realtime. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

No description available.

abstract: The upstream transmission of bulk data files in Ethernet passive optical networks (EPONs) arises from a number of applications, such as data back-up and multimedia file upload. Existing upstream transmission approaches lead to severe delays for conventional packet traffic when best-effort file and packet traffic are mixed. I propose and evaluate an exclusive interval for bulk transfer (EIBT) transmission strategy that reserves an EIBT for file traffic in an EPON polling cycle. I optimize the duration of the EIBT to minimize a weighted sum of packet and file delays. Through mathematical delay analysis and verifying simulation, it is demonstrated that the EIBT approach preserves small delays for packet traffic while efficiently serving bulk data file transfers. Dynamic circuits are well suited for applications that require predictable service with a constant bit rate for a prescribed period of time, such as demanding e-science applications. Past research on upstream transmission in passive optical networks (PONs) has mainly considered packet-switched traffic and has focused on optimizing packet-level performance metrics, such as reducing mean delay. This study proposes and evaluates a dynamic circuit and packet PON (DyCaPPON) that provides dynamic circuits along with packet-switched service. DyCaPPON provides (i) flexible packet-switched service through dynamic bandwidth allocation in periodic polling cycles, and (ii) consistent circuit service by allocating each active circuit a fixed-duration upstream transmission window during each fixed-duration polling cycle. I analyze circuit-level performance metrics, including the blocking probability of dynamic circuit requests in DyCaPPON through a stochastic knapsack-based analysis. Through this analysis I also determine the bandwidth occupied by admitted circuits. The remaining bandwidth is available for packet traffic and I analyze the resulting mean delay of packet traffic. Through extensive numerical evaluations and verifying simulations, the circuit blocking and packet delay trade-offs in DyCaPPON is demonstrated. An extended version of the DyCaPPON designed for light traffic situation is introduced in this article as well. / Dissertation/Thesis / Ph.D. Electrical Engineering 2014

Os sistemas dinamicamente reconfiguráveis (SDRs) são uma alternativa para o desenvolvimento de sistemas sobre silício baseados em circuitos programáveis (SoPC), cujo principal beneficio é o bom aproveitamento da área do dispositivo. Sendo neles implementados circuitos que representam as tarefas que devem operar numa etapa específica do tempo de operação do sistema, permitem um menor consumo de área e de energia, parâmetros importantes nos sistemas portáveis. Isto tem gerado muito interesse no que se refere às metodologias de projeto utilizando FPGAs (Field Programmable Gate Arrays) dinamicamente reconfiguráveis (DRFPGAs) e à definição de um meio de comunicação estruturado para tratar da transferência de dados entre as partes reconfiguráveis e as fixas, mas estas tarefas, assim como a concretização de sua comunicação, seguem sendo ainda essencialmente manuais, devido à falta de metodologias de projeto e ferramentas de CAD que simplifiquem o projeto de SDRs. Este trabalho foca uma das limitações mais efetivas para a adoção da reconfiguração dinâmica: a falta de ferramentas de CAD que suportem o projeto de SDRs, inclusive os baseados em redes intra-chip (NoCs), em particular, no posicionamento dos módulos. Neste trabalho, uma arquitetura para SDRs baseado em NoCs é proposta e um algoritmo de posicionamento dos módulos de um SDR baseado em aspectos reais da família do DRFPGAs é desenvolvido, dentro de uma ferramenta denominada DynoPlace. Desenvolveu-se também um modelo de validação e simulação de SDRs, em tempo de operação, utilizando-se a técnica de chaveamento dinâmico de circuitos. Para o estudo do caso, de validação da arquitetura e metodologia, propõe-se uma aplicação teste baseada em computação de operações aritméticas. A metodologia de simulação permite determinar o tempo da reconfiguração e verificar o comportamento do SDR no momento da reconfiguração. A ferramenta DynoPlace permite gerar os arquivos de restrição de usuário (UCF) de posicionamento dos módulos do SDR no DRFPGA Virtex-4LX25. Este contém informações do posicionamento dos módulos do sistema, dos dispositivos usados para as entradas e saídas do sistema além do posicionamento dos bus-macros. Com os arquivos gerados pela metodologia e ferramenta DynoPlace, pode-se executar com sucesso os scripts da metodologia Early Access da Xilinx para gerar o SDR de forma automática. / Dynamically Reconfigurable Systems (DRSs) are an alternative for developing Systems on a Programmable Chip (SoPC), being the efficient use of device\'s area one of its main advantages. Circuits implemented as DRSs represent tasks which must be active in specific times into the system operation, allowing area and energy saving, which is an important goal for portable systems. This has generated interests on the design methodology using Dynamically Reconfigurable Field Programmable Gate Arrays (DRFPGAs) and on the definition of communication systems for handling data transfer between static and reconfigurable partitions. However, these tasks, as well as the communication structure, are still carried out manually due to lack of design methodologies and CAD tools applied to DRSs design. This work focuses on the one of main drawbacks to the adoption of dynamic reconfiguration methods: the absence of CAD tools which support DRS designs, specifically, in the module positioning task, included, for those based on Network-on-Chip (NoCs). In this work, an architecture for DRSs based on NoCs is presented and an algorithm for module positioning is developed in a tool called DynoPlace as well, based on real specifications of DRFPGAs families. It is also developed a run-time simulation and validation model for DRSs, through a dynamic circuit switching technique. For the validation of architecture and methodology study case, an application test based on arithmetic operations has been proposed. The simulations methodology allows to determine the reconfiguration time and verify the DRS behavior at the moment of reconfiguration. The DynoPlace tool allows to generate User Constraint File (UCF) of DRS\'s modules positioning for the DRFPGA Virtex-4LX25. This file contains information of modules positioning in the system, of the devices used for inputs and outputs of the system, and the positioning of bus-macros. After the files generation by the methodology, and the DynoPlace tool, it is possible to successfully execute the Early Access scripts for generating the DRS automatically.

Os sistemas dinamicamente reconfiguráveis (SDRs) são uma alternativa para o desenvolvimento de sistemas sobre silício baseados em circuitos programáveis (SoPC), cujo principal beneficio é o bom aproveitamento da área do dispositivo. Sendo neles implementados circuitos que representam as tarefas que devem operar numa etapa específica do tempo de operação do sistema, permitem um menor consumo de área e de energia, parâmetros importantes nos sistemas portáveis. Isto tem gerado muito interesse no que se refere às metodologias de projeto utilizando FPGAs (Field Programmable Gate Arrays) dinamicamente reconfiguráveis (DRFPGAs) e à definição de um meio de comunicação estruturado para tratar da transferência de dados entre as partes reconfiguráveis e as fixas, mas estas tarefas, assim como a concretização de sua comunicação, seguem sendo ainda essencialmente manuais, devido à falta de metodologias de projeto e ferramentas de CAD que simplifiquem o projeto de SDRs. Este trabalho foca uma das limitações mais efetivas para a adoção da reconfiguração dinâmica: a falta de ferramentas de CAD que suportem o projeto de SDRs, inclusive os baseados em redes intra-chip (NoCs), em particular, no posicionamento dos módulos. Neste trabalho, uma arquitetura para SDRs baseado em NoCs é proposta e um algoritmo de posicionamento dos módulos de um SDR baseado em aspectos reais da família do DRFPGAs é desenvolvido, dentro de uma ferramenta denominada DynoPlace. Desenvolveu-se também um modelo de validação e simulação de SDRs, em tempo de operação, utilizando-se a técnica de chaveamento dinâmico de circuitos. Para o estudo do caso, de validação da arquitetura e metodologia, propõe-se uma aplicação teste baseada em computação de operações aritméticas. A metodologia de simulação permite determinar o tempo da reconfiguração e verificar o comportamento do SDR no momento da reconfiguração. A ferramenta DynoPlace permite gerar os arquivos de restrição de usuário (UCF) de posicionamento dos módulos do SDR no DRFPGA Virtex-4LX25. Este contém informações do posicionamento dos módulos do sistema, dos dispositivos usados para as entradas e saídas do sistema além do posicionamento dos bus-macros. Com os arquivos gerados pela metodologia e ferramenta DynoPlace, pode-se executar com sucesso os scripts da metodologia Early Access da Xilinx para gerar o SDR de forma automática. / Dynamically Reconfigurable Systems (DRSs) are an alternative for developing Systems on a Programmable Chip (SoPC), being the efficient use of device\'s area one of its main advantages. Circuits implemented as DRSs represent tasks which must be active in specific times into the system operation, allowing area and energy saving, which is an important goal for portable systems. This has generated interests on the design methodology using Dynamically Reconfigurable Field Programmable Gate Arrays (DRFPGAs) and on the definition of communication systems for handling data transfer between static and reconfigurable partitions. However, these tasks, as well as the communication structure, are still carried out manually due to lack of design methodologies and CAD tools applied to DRSs design. This work focuses on the one of main drawbacks to the adoption of dynamic reconfiguration methods: the absence of CAD tools which support DRS designs, specifically, in the module positioning task, included, for those based on Network-on-Chip (NoCs). In this work, an architecture for DRSs based on NoCs is presented and an algorithm for module positioning is developed in a tool called DynoPlace as well, based on real specifications of DRFPGAs families. It is also developed a run-time simulation and validation model for DRSs, through a dynamic circuit switching technique. For the validation of architecture and methodology study case, an application test based on arithmetic operations has been proposed. The simulations methodology allows to determine the reconfiguration time and verify the DRS behavior at the moment of reconfiguration. The DynoPlace tool allows to generate User Constraint File (UCF) of DRS\'s modules positioning for the DRFPGA Virtex-4LX25. This file contains information of modules positioning in the system, of the devices used for inputs and outputs of the system, and the positioning of bus-macros. After the files generation by the methodology, and the DynoPlace tool, it is possible to successfully execute the Early Access scripts for generating the DRS automatically.