Thèse (D.Eng.) -- Université du Québec à Chicoutimi, 2007. / La p. de t. porte en outre: Thèse présentée à l'Université du Québec à Chicoutimi comme exigence partielle du doctorat en ingénierie. CaQQUQ Bibliogr.: f. 222-239. Document électronique également accessible en format PDF. CaQQUQ

Thèse (D.Eng.) -- Université du Québec à Chicoutimi, 2007. / La p. de t. porte en outre: Thèse présentée à l'Université du Québec à Chicoutimi comme exigence partielle du doctorat en ingénierie. CaQQUQ Bibliogr.: f. 222-237. Document électronique également accessible en format PDF. CaQQUQ

Thèse (D.Eng.)--Université du Québec à Chicoutimi, 2000. / Document électronique également accessible en format PDF. CaQCU

Doctorat en Sciences / info:eu-repo/semantics/nonPublished

No description available.

Electron densities and collision frequencies were obtained on a number of gases in a dc discharge at low pressures (0.70-2mm of Hg). These measurements were performed by microwave probing of a filament of the dc discharge placed coaxially in a resonant cavity operating in a TM₀₁₀ mode. The equipment and techniques for making the microwave measurements employing the resonant cavity are described. One of the main features of this investigation is the technique of differentiating the resonance signal of the loaded cavity in order to make accurate measurements of the resonant frequency and half-power point frequencies.

Electrostatic Discharge (ESD) phenomenon happens everywhere in our daily life. And it can occurs through the whole lifespan of an Integrated Circuit (IC), from the early wafer fabrication process, extending to assembly operation, and finally ending at the user‟s site. It has been reported that up to 35% of total IC field failures are ESD-induced, with estimated annual costs to the IC industry running to several billion dollars. The most straightforward way to avoid the ICs suffering from the threatening of ESD damages is to develop on-chip ESD protection circuits which can afford a robust, low-impedance bypassing path to divert the ESD current to the ground. There are three different types of popular ESD protection devices widely used in the industry, and they are diodes or diodes string, Grounded-gate NMOS (GGNMOS) and Silicon Controlled Rectifier (SCR). Among these different protection solutions, SCR devices have the highest ESD current conduction capability due to the conductivity modulation effect. But SCR devices also have several shortcomings such as the higher triggering point, the lower clamping voltage etc, which will become obstacles for SCR to be widely used as an ESD protection solutions in most of the industry IC products. At first, in some applications with pin voltage goes below ground or above the VDD, dual directional protection between each two pins are desired. The traditional dual-directional SCR structures will consume a larger silicon area or lead to big leakage current issue due to the happening of punch-through effect. A new and improved SCR structure for low-triggering ESD iv applications has been proposed in this dissertation and successfully realized in a BiCMOS process. Such a structure possesses the desirable characteristics of a dual-polarity conduction, low trigger voltage, small leakage current, large failing current, adjustable holding voltage, and compact size. Another issue with SCR devices is its deep snapback or lower holding voltage, which normally will lead to the latch-up happen. To make SCR devices be immunity with latch-up, it is required to elevate its holding voltage to be larger than the circuits operational voltage, which can be several tens volts in modern power electronic circuits. Two possible solutions have been proposed to resolve this issue. One solution is accomplished by using a segmented emitter topology based on the concept that the holding voltage can be increased by reducing the emitter injection efficiency. Experimental data show that the new SCR can posses a holding voltage that is larger than 40V and a failure current It2 that is higher than 28mA/um. The other solution is accomplished by stacking several low triggering voltage high holding voltage SCR cells together. The TLP measurement results show that this novel SCR stacking structure has an extremely high holding voltage, very small snapback, and acceptable failure current. The High Holding Voltage Figure of Merit (HHVFOM) has been proposed to be a criterion for different high holding voltage solutions. The HHVFOM comparison of our proposed structures and the existing high holding voltage solutions also show the advantages of our work.

Electrostatic discharge (ESD) is defined as the transfer of charge between bodies at different potentials. The electrostatic discharge induced integrated circuit damages occur throughout the whole life of a product from the manufacturing, testing, shipping, handing, to end user operating stages. This is particularly true as microelectronics technology continues shrink to nano-metric dimensions. The ESD related failures is a major IC reliability concern and results in a loss of millions dollars to the semiconductor industry each year. Several ESD stress models and test methods have been developed to reproduce the real world ESD discharge events and quantify the sensitivity of ESD protection structures. The basic ESD models are: Human body model (HBM), Machine model (MM), and Charged device model (CDM). To avoid or reduce the IC failure due to ESD, the on-chip ESD protection structures and schemes have been implemented to discharge ESD current and clamp overstress voltage under different ESD stress events. Because of its simple structure and good performance, the junction diode is widely used in on-chip ESD protection applications. This is particularly true for ESD protection of lowvoltage ICs where a relatively low trigger voltage for the ESD protection device is required. However, when the diode operates under the ESD stress, its current density and temperature are far beyond the normal conditions and the device is in danger of being damaged. For the design of effective ESD protection solution, the ESD robustness and low parasitic capacitance are two major concerns. The ESD robustness is usually defined after the failure current It2 and on-state resistance Ron. The transmission line pulsing (TLP) measurement is a very effective tool for evaluating the ESD robustness of a circuit or single element. This is particularly helpful in iv characterizing the effect of HBM stress where the ESD-induced damages are more likely due to thermal failures. Two types of diodes with different anode/cathode isolation technologies will be investigated for their ESD performance: one with a LOCOS (Local Oxidation of Silicon) oxide isolation called the LOCOS-bound diode, the other with a polysilicon gate isolation called the polysilicon-bound diode. We first examine the ESD performance of the LOCOS-bound diode. The effects of different diode geometries, metal connection patterns, dimensions and junction configurations on the ESD robustness and parasitic capacitance are investigated experimentally. The devices considered are N+/P-well junction LOCOS-bound diodes having different device widths, lengths and finger numbers, but the approach applies generally to the P+/N-well junction diode as well. The results provide useful insights into optimizing the diode for robust HBM ESD protection applications. Then, the current carrying and voltage clamping capabilities of LOCOS- and polysiliconbound diodes are compared and investigated based on both TCAD simulation and experimental results. Comparison of these capabilities leads to the conclusion that the polysilicon-bound diode is more suited for ESD protection applications due to its higher performance. The effects of polysilicon-bound diode’s design parameters, including the device width, anode/cathode length, finger number, poly-gate length, terminal connection and metal topology, on the ESD robustness are studied. Two figures of merits, FOM_It2 and FOM_Ron, are developed to better assess the effects of different parameters on polysilicon-bound diode’s overall ESD performance. As latest generation package styles such as mBGAs, SOTs, SC70s, and CSPs are going to the millimeter-range dimensions, they are often effectively too small for people to handle with fingers. The recent industry data indicates the charged device model (CDM) ESD event becomes v increasingly important in today’s manufacturing environment and packaging technology. This event generates highly destructive pulses with a very short rise time and very small duration. TLP has been modified to probe CDM ESD protection effectiveness. The pulse width was reduced to the range of 1-10 ns to mimic the very fast transient of the CDM pulses. Such a very fast TLP (VFTLP) testing has been used frequently for CDM ESD characterization. The overshoot voltage and turn-on time are two key considerations for designing the CDM ESD protection devices. A relatively high overshoot voltage can cause failure of the protection devices as well as the protected devices, and a relatively long turn-on time may not switch on the protection device fast enough to effectively protect the core circuit against the CDM stress. The overshoot voltage and turn-on time of an ESD protection device can be observed and extracted from the voltage versus time waveforms measured from the VFTLP testing. Transient behaviors of polysilicon-bound diodes subject to pulses generated by the VFTLP tester are characterized for fast ESD events such as the charged device model. The effects of changing devices’ dimension parameters on the transient behaviors and on the overshoot voltage and turn-on time are studied. The correlation between the diode failure and poly-gate configuration under the VFTLP stress is also investigated. Silicon-controlled rectifier (SCR) is another widely used ESD device for protecting the I/O pins and power supply rails of integrated circuits. Multiple fingers are often needed to achieve optimal ESD protection performance, but the uniformity of finger triggering and current flow is always a concern for multi-finger SCR devices operating under the post-snapback region. Without a proper understanding of the finger turn-on mechanism, design and realization of robust SCRs for ESD protection applications are not possible. Two two-finger SCRs with different combinations of anode/cathode regions are considered, and their finger turn-on vi uniformities are analyzed based on the I-V characteristics obtained from the transmission line pulsing (TLP) tester. The dV/dt effect of pulses with different rise times on the finger turn-on behavior of the SCRs are also investigated experimentally. In this work, unless noted otherwise, all the measurements are conducted using the Barth 4002 transmission line pulsing (TLP) and Barth 4012 very-fast transmission line pulsing (VFTLP) testers.

Today, ESD is a major consideration in the design and manufacture of ICs. ESD problems are increasing in the electronics industry because of the increasing trend toward higher speed and smaller device sizes. There is growing interest in knowing the effects of ESD protection circuit on the performance of semiconductor integrated circuits (ICs) because of the impact it has on core RF circuit performance. This study investigated the impact of ESD protection circuit on RF Power amplifiers. Even though ESD protection for digital circuits has been known for a while, RF-ESD is a challenge. From a thorough literature search on prior art ESD protection circuits, Silicon controlled rectifier was found to be most effective and reliable ESD protection for power amplifier circuit. A SCR based ESD protection was used to protect the power amplifier and a model was developed to gain better understanding of ESD protected power amplifiers. Simulated results were compared and contrasted against theoretically derived equations. A 5.2GHz fully ESD protected Class AB power amplifier was designed and simulated using TSMC 0.18 um technology. Further, the ESD protection circuit was added to a cascoded Class-E power amplifier operating at 5.2 GHz. ADS simulation results were used to analyze the PA’s RF performance degradation. Various optimization techniques were used to improve the RF circuit performance.

A methodology to obtain design guidelines for gate oxide input pin protection and high voltage output pin protection in Electrostatic Discharge (ESD) time frame is developed through measurements and Technology Computer Aided Design (TCAD). A set of parameters based on transient measurements are used to define Transient Safe Operating Area (TSOA). The parameters are then used to assess effectiveness of protection devices for output and input pins. The methodology for input pins includes establishing ESD design targets under Charged Device Model (CDM) type stress in low voltage MOS inputs. The methodology for output pins includes defining ESD design targets under Human Metal Model (HMM) type stress in high voltage Laterally Diffused MOS (LDMOS) outputs. First, the assessment of standalone LDMOS robustness is performed, followed by establishment of protection design guidelines. Secondly, standalone clamp HMM robustness is evaluated and a prediction methodology for HMM type stress is developed based on standardized testing. Finally, LDMOS and protection clamp parallel protection conditions are identified