Thesis (Ph. D.)--University of Wisconsin--Madison, 1957. / Typescript. Vita. eContent provider-neutral record in process. Description based on print version record. Bibliography: leaves 122-128.

No description available.

Call number: LD2668 .T4 1936 S31

Reactive power compensation, as generated by capacitors, has been used to mitigate the constraints of power transmission and improve the power transfer of the transmission system of the South African power utility, Eskom‟s 66/22kV Albany-Wesley transmission system. An investigation was carried out on a number of current compensation schemes, and their operations, by means of load flow analysis. Different capacitor qualities and technologies were applied to alter the transmission line characteristics that resulted in acceptable voltage regulation. This resulted in easing the load on the lines and transformers and hence reducing line losses. For long transmission lines, utilities need voltage support, as provided for by different voltage compensators, to keep the terminal voltage within standard voltage regulation, and meet the designed power demand. The approach to large and small scale compensation was tested and the outcomes revealed distinct patterns that were used to confirm the hypothesis and improve the transfer of power. The templating temperature and thermal perspective as used by Eskom on line design was discussed and used to design a new transmission line. Load flow solutions were also used to plan and design the optimised transmission system as well as to determine the specification and location of the compensating capacitor banks. Capacitor banks, as a source of reactive power, were used to model the compensation in this research. Electrical protection and faults associated with the capacitors banks were discussed, as prevention to total blackout or load shedding on the transmission line in case of established contingency. Long term investment plans, to meet future electricity demands, require substantial investment hence a financial survey was carried out. Finally this dissertation selects a viable solution to meet the electrical power demands and then recommends a way forward for the Eskom‟s 66/22kV Albany-Wesley line.

No description available.

No description available.

Thesis (M.S.)--Oregon State University, 2011. / Printout. Includes bibliographical references (leaves 85-91). Also available on the World Wide Web.

M.Ing. / This study focuses its attention on conducted common mode EMI. Common mode current is the current that flows from an electrical circuit to a zero reference plane and back to the circuit again. It is known that the manner in which the common mode current flows is through stray capacitances that form between the electrical circuit and the zero reference. This study was aimed at developing a method to measure the value of the stray capacitance of a switching circuit. Determining the value of the stray capacitance by taking physical measurements on a circuit board is a challenge for a number of reasons, one of which is that great care should be taken not to add to the stray capacitance by means of the measuring equipment. By measuring the value of the stray capacitance, it will be possible to model the occurrence of Common Mode EMI better and more accurately. This could, in turn, lead to a reduction in EMI. Any body of an arbitrary shape, size and material exhibits a self-capacitance with respect to a zero reference frame. This principle, together with the principle of conservation of charge, also applies to electrical components, or circuits as a whole. The experimental work was performed on a buck DC-DC converter. The circuit was simplified to aid in analysis. By varying the value of an external capacitance and taking basic measurements, it is then possible to uniquely determine the absolute values of the self-capacitances. For every pair of external capacitance values placed in the circuit (of which one can be =0pF), a value for stray capacitance is calculated. Many data points were recorded with many different external capacitors in the circuit, resulting in a variety of stray capacitance values. In order to obtain a single value, a weighted mean of all the values was calculated. The values obtained in this proposed method of measuring the stray capacitance compares well with that obtained using the Finite Element Method. The advantage of the method presented here is that the self-capacitances are determined under the actual operational conditions, no specialised equipment is required and no unique handling of parasitics is needed. The method relies on very simple measurements and no complex data manipulations are required.

Electrostatic discharge (ESD) is defined as the transfer of charge between bodies at different potentials. The electrostatic discharge induced integrated circuit damages occur throughout the whole life of a product from the manufacturing, testing, shipping, handing, to end user operating stages. This is particularly true as microelectronics technology continues shrink to nano-metric dimensions. The ESD related failures is a major IC reliability concern and results in a loss of millions dollars to the semiconductor industry each year. Several ESD stress models and test methods have been developed to reproduce the real world ESD discharge events and quantify the sensitivity of ESD protection structures. The basic ESD models are: Human body model (HBM), Machine model (MM), and Charged device model (CDM). To avoid or reduce the IC failure due to ESD, the on-chip ESD protection structures and schemes have been implemented to discharge ESD current and clamp overstress voltage under different ESD stress events. Because of its simple structure and good performance, the junction diode is widely used in on-chip ESD protection applications. This is particularly true for ESD protection of lowvoltage ICs where a relatively low trigger voltage for the ESD protection device is required. However, when the diode operates under the ESD stress, its current density and temperature are far beyond the normal conditions and the device is in danger of being damaged. For the design of effective ESD protection solution, the ESD robustness and low parasitic capacitance are two major concerns. The ESD robustness is usually defined after the failure current It2 and on-state resistance Ron. The transmission line pulsing (TLP) measurement is a very effective tool for evaluating the ESD robustness of a circuit or single element. This is particularly helpful in iv characterizing the effect of HBM stress where the ESD-induced damages are more likely due to thermal failures. Two types of diodes with different anode/cathode isolation technologies will be investigated for their ESD performance: one with a LOCOS (Local Oxidation of Silicon) oxide isolation called the LOCOS-bound diode, the other with a polysilicon gate isolation called the polysilicon-bound diode. We first examine the ESD performance of the LOCOS-bound diode. The effects of different diode geometries, metal connection patterns, dimensions and junction configurations on the ESD robustness and parasitic capacitance are investigated experimentally. The devices considered are N+/P-well junction LOCOS-bound diodes having different device widths, lengths and finger numbers, but the approach applies generally to the P+/N-well junction diode as well. The results provide useful insights into optimizing the diode for robust HBM ESD protection applications. Then, the current carrying and voltage clamping capabilities of LOCOS- and polysiliconbound diodes are compared and investigated based on both TCAD simulation and experimental results. Comparison of these capabilities leads to the conclusion that the polysilicon-bound diode is more suited for ESD protection applications due to its higher performance. The effects of polysilicon-bound diode’s design parameters, including the device width, anode/cathode length, finger number, poly-gate length, terminal connection and metal topology, on the ESD robustness are studied. Two figures of merits, FOM_It2 and FOM_Ron, are developed to better assess the effects of different parameters on polysilicon-bound diode’s overall ESD performance. As latest generation package styles such as mBGAs, SOTs, SC70s, and CSPs are going to the millimeter-range dimensions, they are often effectively too small for people to handle with fingers. The recent industry data indicates the charged device model (CDM) ESD event becomes v increasingly important in today’s manufacturing environment and packaging technology. This event generates highly destructive pulses with a very short rise time and very small duration. TLP has been modified to probe CDM ESD protection effectiveness. The pulse width was reduced to the range of 1-10 ns to mimic the very fast transient of the CDM pulses. Such a very fast TLP (VFTLP) testing has been used frequently for CDM ESD characterization. The overshoot voltage and turn-on time are two key considerations for designing the CDM ESD protection devices. A relatively high overshoot voltage can cause failure of the protection devices as well as the protected devices, and a relatively long turn-on time may not switch on the protection device fast enough to effectively protect the core circuit against the CDM stress. The overshoot voltage and turn-on time of an ESD protection device can be observed and extracted from the voltage versus time waveforms measured from the VFTLP testing. Transient behaviors of polysilicon-bound diodes subject to pulses generated by the VFTLP tester are characterized for fast ESD events such as the charged device model. The effects of changing devices’ dimension parameters on the transient behaviors and on the overshoot voltage and turn-on time are studied. The correlation between the diode failure and poly-gate configuration under the VFTLP stress is also investigated. Silicon-controlled rectifier (SCR) is another widely used ESD device for protecting the I/O pins and power supply rails of integrated circuits. Multiple fingers are often needed to achieve optimal ESD protection performance, but the uniformity of finger triggering and current flow is always a concern for multi-finger SCR devices operating under the post-snapback region. Without a proper understanding of the finger turn-on mechanism, design and realization of robust SCRs for ESD protection applications are not possible. Two two-finger SCRs with different combinations of anode/cathode regions are considered, and their finger turn-on vi uniformities are analyzed based on the I-V characteristics obtained from the transmission line pulsing (TLP) tester. The dV/dt effect of pulses with different rise times on the finger turn-on behavior of the SCRs are also investigated experimentally. In this work, unless noted otherwise, all the measurements are conducted using the Barth 4002 transmission line pulsing (TLP) and Barth 4012 very-fast transmission line pulsing (VFTLP) testers.

Several approaches have been used to develop carbon nanotube (CNT) based electrochemical supercapacitors. These approaches include the following: (a) stabilization and carbonization of ternary composites of polyacrylonitrile (PAN), poly (styrene co-acrylonitrile) (SAN) copolymer, and single wall carbon nanotubes (SWNTs); (b) SWNT membranes functionalized with aryl chloride, sodium sulfonate, aryl sulfonic acid, bis(3,5-di-tert-butylphenyl)5-aminobenzene-1,3-dioate, and 4,4 -methylenedianiline; and (c) pyrrole treated SWNTs. In addition nitric acid functionalized and heat-treated SWNT membranes have been studied. The electrochemical supercapacitor behavior of these membrane electrodes has been characterized by cyclic voltammetry, constant current charging-discharging, and impedance analysis in aqueous and ionic liquid electrolytes. Long term performance of selected electrodes has been evaluated. The surface area and pore size distribution was quantified by N2 gas adsorption/desorption and correlated with capacitance performance. The surface functional groups have been characterized by X-ray photoelectron spectroscopy. CNT electrode/electrolyte interaction has been characterized using contact angle measurements. Electrolyte absorption by the electrodes has also been characterized. Carbonized PAN/SAN/SWNT ternary composites exhibit double layer capacity of over 200 μF/cm2. By comparison, the double layer capacity of classical meso-porous carbons is in the range of 10-50 μF/cm2. The capacitance of functionalized SWNTs is up to 2 times that of the control bucky paper made from unfunctionalized SWNTs. Energy density of functionalized electrodes when evaluated in an ionic liquid is as high as 28 kJ/kg. High capacitance (up to 350 F/g) was obtained for pyrrole-treated functionalized SWNT membranes in 6 M KOH. This value is almost seven times that of the control bucky paper. Correlating the capacitance with surface area and pore size distribution, it was observed that macropores (pore width greater than 50 nm) play an important role for achieving high capacitance.