Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1993. / Vita. Abstract. Includes bibliographical references (leaves 38-39). Also available via the Internet.

An algorithm is derived for the removal of the DC offset from a faulted current signal using a microprocessor sampling on real-time. The algorithm is to be used instead of the analog Mimic circuit in distance computer relaying. Four variations of the algorithm were derived and tested to determine the best compromise between time response and noise sensitivity. The relay hardware is taken into consideration for the derivations to avoid adding any hardware to the relay. The graphical results of the test run in an analog simulator at the Virginia Tech Power Systems Laboratory are presented. Faults at different voltage angles were performed to determine the algorithm's performance at different levels of DC offset. From the graphical response obtained from the test and taking into consideration hardware and software limitations, a preferred algorithm is selected with a good compromise between time response and noise sensitivity. / Master of Science

Guided probe testing of printed circuit boards is a technique that has been well developed by automatic test equipment manufacturers to pinpoint faults. Though the guided probe technique of testing printed circuit boards is a process capable of providing high diagnostic resolution, the technique is inefficient when it is performed manually. The throughput of board testing is bottlenecked because of the time required for an operator to manually move a probe to a specific location on the board under test in order to measure a stimulated response. Integration of a CAD driven X-Y prober is a way to automate guided probe testing of printed circuit boards. This research integrates a personal computer based automated guided probe testing system. A CAD tool provides geometric and circuit connectivity information. Automatic test generation, CAD information post processing, and automatic guided probe testing software tools are developed to implement the system. The ultimate result is increased circuit board test station throughput. This makes the circuit board manufacturing process more efficient and less expensive while maintaining high quality products through more extensive testing. / Master of Science

This dissertation investigates the implementation of S-parameter based network techniques for the analysis of multiconductor, high speed VLSI integrated circuit and packaging interconnects. The S-parameters can be derived from three categories of input parameters: (1) lossy quasi-static R,L,C and G, (2) lossy frequency dependent (dispersive) R,L,C,G and (3) the propagation constants, Γ, the characteristic impedance, Z(c) and the conductor eigencurrents, I, derived from full wave analysis. The S-parameter network techniques developed allow for: the analysis of periodic waveform excitation, the incorporation of externally measured or calculated scattering parameter data and large system analysis through macro decomposition. The inclusion of non-linear terminations has also been developed.

The performance of SPICE and Network C (NC) circuit simulator when simulating MOS transistor circuits has been investigated and compared. SPICE analog model, NC analog model and NC MOS_PWL model are the three MOS transistor models being used. The comparison between SPICE and NC includes five areas. They are MOS transistor model, circuit analysis and computational methods, limitation on the ability to simulate circuits containing the MOS transistor diode configuration, run time and the ability to build new circuit component models using derived equations.

No description available.

Thesis (M.App.Sc.) - Carleton University, 2007. / Includes bibliographical references (p. 106-108). Also available in electronic format on the Internet.

This work examines and implements two different techniques for the estimation of the capacitance and impedance of microstrip-like open structures. Both theories, one developed by Yamashita and Mittra and the other by Itoh and Hebert are based on variational methods. The results for the capacitance and impedance of a microstrip-like structure are calculated numerically and compared with measurements taken using a sample. The results presented in this thesis indicate that the first method produces results with large error and it can be used for microstrip structures with only one strip. The second method produces very accurate results for the microstrip structure under consideration and is the one recommended. / Master of Science

An automatic method generates tests for circuits described in a hardware description language (HDL). The input description is in a non-procedural subset of VHDL, with a simplified period-oriented timing model. The fault model, based on previous research, includes micro-operation and control statement faults. The test method uses path-tracing, working directly from the circuit description, not a derived graph or table. Artificial intelligence problem-solving techniques of goals and goal solving are used to represent and manipulate sensitization, justification, and propagation requirements. Backtracking is used to recover from incorrect choices. The method is implemented in ProLog, an artificial intelligence language. Results of this experimental ProLog implementation are summarized and analyzed for strengths and weaknesses of the test method. Suggestions are included to counter the weaknesses. A user's manual is included for the experimental implementation. / M.S.

No description available.