Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2002. / Includes bibliographical references. Also available in electronic version. Access restricted to campus users.

Thesis (Ph. D.)--University of Washington, 1996. / Vita. Includes bibliographical references (leaves [70]-74).

The proposed hybrid system generates AC power by combining solar and wind energy converted by a doubly-fed induction generator (DFIG). The DFIG, driven by a wind turbine, needs rotor excitation so the stator can supply a load or the grid. In a variable-speed wind energy system, the stator voltage and its frequency vary with wind speed, and in order to keep them constant, variable-voltage and variable-frequency rotor excitation is to be provided. A power conversion unit supplies the rotor, drawing power either from AC mains or from a PV panel depending on their availability. It consists of a multilevel inverter which gives lower harmonic distortion in the stator voltage. Maximum power point tracking techniques have been implemented for both wind and solar power. The complete hybrid renewable energy system is implemented in a PSIM-Simulink interface and the wind energy conversion portion is realized in hardware using dSPACE controller board.

The integrated high-quality rectifier-regulators [1] are not practical for universal input voltage and wide load range applications because of high bulk-capacitor voltage stress at lighter loads. This load-dependent characteristic of the bulk-capacitor voltage is due to the integration of a discontinuous conduction mode boost converter and a continuous conduction mode dc-dc converter. In addition, this power factor correction technique suffers from a high-voltage spike on the switch at turn-off. In this thesis, variable frequency control, swinging choke, and low loss LC snubber techniques are proposed to alleviate these problems. Finally, several experimental converters with different specifications are evaluated with respect to efficiency and ability to meet the IEC555-2 standards. / Master of Science

Finally, the PSRR performance of LDO is studied. An energy-efficient embedded ripple feed-forward path is proposed to improve the PSRR of LDO. Comparing with some state-of-the-art techniques for PSRR improvement, the proposed LDO features very simple structure thus low-power consumption. A LDO implemented in 0.18-mum CMOS technology with 0.042-mm2 active area has been designed to verify the idea. With an external 4.7-muF output capacitor, in the maximum load condition (i.e. at 25 mA), the PSRR is -77 dB at 1 MHz, -85 dB at 2.5 MHz and -55 dB at 5 MHz, respectively. The quiescent current is 15 muA only, while the transient voltage overshoot or undershoot is less than 40 mV when load current changes between 1 mA and 25 mA with 40-ns step time. The LDO achieves good line and load regulations of 3 mV/V and 50 muV/mA, respectively. / Remotely- or battery-powered wireless system-on-a-chip (SoC) needs energy-efficient and high-integration power-management solutions due to their energy-aware characteristics. Low-dropout regulator (LDO) is a good solution because of its excellent performances such as low power consumption, fast load-transient response and high power-supply ripple rejection (PSRR). Moreover, it is easy to be fully integrated since no inductor is needed to be the energy-storage element. Recent development of output-capacitorless LDO (OCL-LDO) realizes on-chip, local voltage regulation to enable more effective integrated power management for SoC. In this thesis, OCL-LDOs with low power consumption and fast load-transient response are investigated and presented in this thesis. LDO with output capacitor for high-PSRR operation to provide clean power supply to RF circuits is also reported. Three LDOs are developed and fabricated to verify the proposed ideas. / The first design is an ultra low-power voltage regulator for remotely powered energy-autonomous devices. It has been fabricated in a commercial 0.18-mum CMOS technology and applied to a passive UHF RFID tag IC. With the low-power voltage reference circuit and sub-threshold operations, the total quiescent current is 700 nA under a 1.8-V power supply. The output voltage of the regulator is 1.45 V with load capability of 50 muA. The temperature coefficients of the voltage reference and the output voltage are only 9 and 43 ppm/°C, respectively. A POR signal with 150-ns-width pulse is also generated to reset the digital processing part in the tag IC. / The second design is a fast-transient OCL-LDO, which has been implemented in a commercial 90-nm CMOS technology. Experimental result verifies that it is stable for a capacitive load from 0 to 50 pF and with load capability of 100 rnA. Moreover, the gain-enhanced structure provides sufficient loop gain to improve line regulation to 3.78 mV/V and load regulation to 0.1 mV/mA, respectively. The embedded voltage-spike detection circuit enables pseudo Class-AB operation to drive the power transistor promptly. The maximum overshoot and undershoot under a 1.2-V supply are less than 66 mV for full load current changes within 100-ns edge time, and the recovery time is less than 5 mus. While the measured power consumption is only 6 muW under a 0.75-V supply. / Guo, Jianping. / Adviser: Ka Nang Leung. / Source: Dissertation Abstracts International, Volume: 73-06, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Ho, Marco. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2013. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Or, Pui Ying. / "July 2010." / Thesis (M.Phil.)--Chinese University of Hong Kong, 2010. / Includes bibliographical references. / Abstracts in English and Chinese. / Acknowledgments / Table of Content / List of Figures / List of Tables / List of Publications / Chapter Chapter 1 - --- Background of LDO Research / Chapter 1.1 --- Structure of a LDO --- p.1-1 / Chapter 1.2 --- Principle of Operation of LDO --- p.1-2 / Chapter 1.3 --- Steady-State Specification of LDO --- p.1-3 / Chapter 1.4 --- High-Frequency Specification of LDO --- p.1-3 / Chapter 1.5 --- Dynamic Specification of LDO --- p.1-4 / Chapter 1.6 --- An Advanced LDO Structure --- p.1-4 / Chapter 1.7 --- Contribution and Outline of the Thesis --- p.1-5 / References --- p.1-6 / Chapter Chapter 2 - --- PSRR Analysis / Chapter 2.1 --- Modeling of the PSRR of LDO --- p.2-3 / Chapter 2.2 --- Analysis of LDO Circuit Using Proposed Modeling --- p.2-6 / Chapter 2.3 --- Conclusion of Chapter --- p.2-12 / References --- p.2-13 / Chapter Chapter 3- --- An Output-Capacitorless LDO with Direct Voltage-Spike Detection / Chapter 3.1 --- Analysis of Output-Capacitorless LDO --- p.3-5 / Chapter 3.2 --- LDO with Proposed Voltage-Spike Detection Circuit --- p.3-7 / Chapter 3.3 --- Experimental Results --- p.3-15 / Chapter 3.4 --- Conclusion of Chapter --- p.3-21 / References --- p.3-22 / Chapter Chapter 4 - --- A LDO with Impedance Adjustment and Loop-Gain Boosting Technique / Chapter 4.1 --- Proposed LDO --- p.4-3 / Chapter 4.2 --- Experimental Results --- p.4-7 / Chapter 4.3 --- Comparison --- p.4-11 / Chapter 4.4 --- Conclusion of Chapter --- p.4-12 / Reference --- p.4-13 / Chapter Chapter 5 - --- Conclusion and Future Work

Includes bibliographical references (p. 143-153).

Thesis (MScEng)--University of Stellenbosch, 2003. / ENGLISH ABSTRACT: This thesis presents the design and implementation of shunt active power filtering algorithms for unbalanced, non-linear loads. A three-phase four-wire topology is developed in the dqO space. Based on this development an accurate dynamic system model, taking into account the effect of the neutral inductor is developed. The synchronous reference frame technique is expanded to enable the isolation of the zero sequence current component into its instantaneous active and reactive current components. Additionally a prediction method is proposed that will enable the proper prediction of the reference currents in a threephase four-wire system. Two categories of reference current signal tracking algorithms are investigated; namely the predictive current controller and the sliding mode current controller. A compensating technique is proposed to compensate for the effects that sampling and computational time delay have on the performance of the system. Additionally, an investigation is done into the effect that dead-time has on the performance of the system, and based on this investigation a dead-time compensating strategy is proposed. Finally simulation and practical results are provided to validate the discussed theories. / AFRIKAANSE OPSOMMING: Hierdie verhandeling ondersoek die ontwerp en implementering van parralel gekoppelde aktiewe filter algoritmes vir ongebalenseerde, nie-lineêre laste. 'n Drie-fase vier-draad topologie, asook 'n korrekte model van die dinamiese sisteem, wat die effek van die neutraal induktor insluit, is ontwikkel in die dqO ruimte. Die sinchroon verwysing vlak tegniek is uitgebrei om die isolering van die nul sekwensie stroom in onderskeidelik die oombliklike aktiewe en reaktiewe stroom komponente te verdeel. Addisioneel is a vooruitskatting tegniek aanbeveel wat die beheerder in staat sal stelom voldoende die verwysing strome vooruit te skat in 'n drie-fase vier-draad stelsel. Twee katagoriee van verwysing stroom volging algoritmes is ondersoek, naamlik die afskatting stroom beheerder en die gleiende modus stroom beheerder. 'n Effektiewe kompensasie tegniek is voorgestel om die effek van tydvertraging as gevolg van monstering en verwerking te elimineer. Addisioneel is die effek van dooie-tyd ondersoek en gebasseer op hierdie ondersoek is 'n effektiewe dooie-tyd kompensasie tegniek voorgestel. Laastens is simulasies en praktiese resultate verskaf om die werking van die voorgestelde teorie te bevestig.

Open-loop stability analysis of multi-loop current-injected switching regulator is performed using a small signal model containing a power stage, an error processor and a duty cycle pulse modulator. Two design constraints and the effects of various critical control circuit parameters are pinpointed and the analysis-based design guidelines are established in order to optimize the switching regulator performances. In addition, an external ramp slope is proposed to obtain the optimal performance and eliminate the 50% duty cycle instability when operated in constant frequency mode. The effects of the second stage output filter are also examined. / Master of Science