Adjustable Speed Drive (ASD) systems are widely used in industry to effectively improve process efficiency and control. Typically, an ASD system consists of a motor with its speed controlled by a power electronics converter via varying the amplitude and frequency of the input voltage. However, several abnormal insulation failures of random wound motors in ASD applications have been reported. These failures were related to voltage transients caused by inverters employing fast insulated Gate Bipolar Transistors (IGBTs) combined with long cables that connect motors to inverters. This thesis further analyzes the distribution of voltage waveforms generated by a pulse-width modulated (PWM) inverter at the motor terminals and windings. Experimental work was performed at the Motor Systems and Resource Facility (MSRF) at Oregon State University on a specially made 5hp induction motor with taps from the first and second coil and from the first four and last two turns in every phase. Tests were performed with long and short cables and results are compared. A simple simulation model was created in PSpice and used to predict maximum voltage transients across coils and turns. The validation of the model is demonstrated by its capability to predict most of the experimental results. / Graduation date: 2000

Indiana University-Purdue University Indianapolis (IUPUI) / The substantial increase demand for electrical energy requires high efficient apparatus dealing with energy conversion. Several technologies have been suggested to implement power supplies with higher efficiency, such as multilevel and interleaved converters. This thesis proposes an energy conversion unit with an optimized number of output voltage levels per number of switches nL=nS. The proposed five-level four-switch per phase converter has nL=nS=5/4 which is by far the best relationship among the converters presented in technical literature. A comprehensive literature review on existing five-level converter topologies is done to compare the proposed topology with conventional multilevel converters. The most important characteristics of the proposed configuration are: (i) reduced number of semiconductor devices, while keeping a high number of levels at the output converter side, (ii) only one DC source without any need to balance capacitor voltages, (iii) high efficiency, (iv) there is no dead-time requirement for the converters operation, (v) leg isolation procedure with lower stress for the DC-link capacitor. Single-phase and three-phase version of the proposed converter is presented in this thesis. Details regarding the operation of the configuration and modulation strategy are presented, as well as the comparison between the proposed converter and the conventional ones. Simulated results are presented to validate the theoretical expectations. In addition a fault tolerant converter based on proposed topology for micro-grid systems is presented. A hybrid pulse-width-modulation for the pre-fault operation and transition from the pre-fault to post-fault operation will be discussed. Selected steady-state and transient results are demonstrated to validate the theoretical modeling.