University of Macau / Faculty of Science and Technology. / Department of Electromechanical Engineering

No description available.

No description available.

No description available.

No description available.

No description available.

No description available.

Digitized by Kansas State University Libraries

Digitized by Kansas Correctional Industries

Chim, Fu Shing. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references (leaves 79-82). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Rewiring Background --- p.4 / Chapter 2.1 --- ATPG-Based Rewiring - REWIRE --- p.5 / Chapter 2.2 --- Graph-Based Rewiring - GBAW --- p.7 / Chapter 3 --- Characteristics of Rewiring Algorithms --- p.10 / Chapter 3.1 --- Comparsion between GBAW and REWIRE --- p.10 / Chapter 3.2 --- Problem Definition and Motivation --- p.11 / Chapter 4 --- Expanding Pattern Library --- p.14 / Chapter 4.1 --- Optimizing GBAW's Pattern Library --- p.14 / Chapter 4.2 --- Reduced Function Set for Gates within Patterns --- p.15 / Chapter 4.3 --- Rewiring with Multiple-Input Gates --- p.15 / Chapter 4.4 --- Experiment with GBAW Rewiring --- p.18 / Chapter 4.4.1 --- Experimental Results --- p.18 / Chapter 4.4.2 --- Discussion --- p.19 / Chapter 4.5 --- Experiment with Multi-way GBAW Partitioning --- p.21 / Chapter 4.5.1 --- Experimental Results --- p.22 / Chapter 4.5.2 --- Discussion --- p.24 / Chapter 4.6 --- Summary --- p.24 / Chapter 5 --- Circuit Structure for Rewiring --- p.26 / Chapter 5.1 --- Common Circuit Structure in GBAW Patterns --- p.26 / Chapter 5.2 --- Single Fanout Chains and Reconverging Alternative Wires for REWIRE --- p.28 / Chapter 5.3 --- Successive Rewiring --- p.31 / Chapter 5.4 --- Summary --- p.33 / Chapter 6 --- Chain-Based Rewiring Approach --- p.35 / Chapter 6.1 --- Single Fanout Chains in Graph-Based Rewiring --- p.35 / Chapter 6.2 --- Chain-Based Rewiring Approach --- p.36 / Chapter 6.3 --- Experimental Results --- p.40 / Chapter 6.4 --- Discussion --- p.41 / Chapter 6.5 --- Summary --- p.43 / Chapter 7 --- Hybrid Rewiring Framework --- p.44 / Chapter 7.1 --- Limit of Static Approaches --- p.44 / Chapter 7.2 --- Analyzing Framework of Dynamic Rewiring --- p.45 / Chapter 7.3 --- Techniques for Redundancy Identification --- p.47 / Chapter 8 --- Hybrid Chain-Based Rewiring Approach --- p.53 / Chapter 8.1 --- Hybrid Rewiring Framework --- p.53 / Chapter 8.1.1 --- Chain-Based Preliminary Target Wire Filtering --- p.55 / Chapter 8.1.2 --- Implication-Based Candidate Wire Generation --- p.55 / Chapter 8.1.3 --- Fast Redundancy Identification --- p.57 / Chapter 8.2 --- Uncontrollability and Controlling-Value Paths --- p.58 / Chapter 8.3 --- HYBRID - An Implementation of Our Framework --- p.61 / Chapter 8.4 --- Experimental Results --- p.63 / Chapter 8.5 --- Discussion --- p.65 / Chapter 8.6 --- Summary --- p.67 / Chapter 9 --- Rewiring Coupled FPGA Technology Mapping --- p.68 / Chapter 9.1 --- FPGA Technology Mapping --- p.68 / Chapter 9.2 --- Rewiring Coupled FPGA Technology Mapping --- p.70 / Chapter 9.2.1 --- Rewiring-based Logic Level Reduction --- p.71 / Chapter 9.2.2 --- Incremental Logic Resynthesis (ILR) Area Minimization --- p.71 / Chapter 9.3 --- Experimental Results --- p.72 / Chapter 9.4 --- Discussion --- p.73 / Chapter 9.5 --- Summary --- p.75 / Chapter 10 --- Conclusion and Future Works --- p.76 / Bibliography --- p.79