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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
61

Arithmetic Logic Unit (ALU) Design Using Reconfigurable CMOS Logic

Srinivasan, Chandra 15 October 2003 (has links)
Using the reconfigurable logic of multi-input floating gate MOSFETs, a 4-bit ALU has been designed for 3V operation. The ALU can perform four arithmetic and four logical operations. Multi- input floating gate (MIFG) transistors have been promising in realizing increased functionality on a chip. A multi- input floating gate MOS transistor accepts multiple inputs signals, calculates the weighted sum of all input signals and then controls the ON and OFF states of the transistor. This enhances the transistor function to more than just switching. This changes the way a logic function can be realized. Implementing a design using multi-input floating gate MOSFETs brings about reduction in transis tor count and number of interconnections. The advantage of bringing down the number of devices is that a design becomes area efficient and power consumption reduces. There are several applications that stress on smaller chip area and reduced power. Multi- input floating gate devices have their use in memories, analog and digital circuits. In the present work we have shown successful implementation of multi- input floating gate MOSFETs in ALU design. A comparison has been made between adders using different design methods w.r.t transistor count. It is seen that our design, implemented using multi-input floating gate MOSFETs, uses the least number of transistors when compared to other designs. The design was fabricated using double polysilicon standard CMOS process by MOSIS in 1.5mm technology. The experimental waveforms and delay measurements have also been presented.
62

Circuitry for a Remotely Powered Bio-Implantable Gastric Electrical Stimulation System

Kona, Satish 14 November 2003 (has links)
Power to bio-implantable devices is usually supplied through a battery implanted with the system or through wires extending to an outside power source. The latter case with wires protruding out of the body can be unaesthetic in appearance and can cause infection. In this research, we consider an alternative way to power a bio-implantable microsystem. It involves using rechargeable lithium batteries. Here, power is delivered remotely to charge implanted battery or batteries. This approach avoids periodic surgery necessary for battery replacement. It also does not tie a person to an external power source at all times. This improves patients quality of life. The present work involves design and fabrication of signal conditioning circuit for a remotely rechargeable, bio-implantable, Battery-powered Electrical Stimulation System (BESS). A rechargeable lithium ion battery with a voltage of 3.7 V powers the proposed circuit. The desired output, which goes directly to the electrodes, is a series of 10 V, 15 mA pulses with a duty cycle of 4.5 %. A second rechargeable lithium ion battery serves as back-up. A lithium ion charging chip is included which is connected to the designed IC through a logic interface. The two batteries work in tandem i.e. when one battery powers the IC the other gets recharged and vice versa thereby providing an uninterruptible output. The IC uses a series of charge pumps to get the required boost in voltage. The IC also includes voltage detector circuits to detect battery voltages, voltage regulator, pulse generator circuits, logic circuits and necessary switches. Individual subsystems of the IC were designed, simulated and fabricated using standard CMOS technology. Individual subsystem circuits were found to work satisfactorily except for the charge pump. A revised design is now under fabrication. The microsystem utilizes a hybrid approach. Experiments done with a bench-top circuit model to simulate the proposed IC showed that a 3 V battery with a capacity of 190 mAh could power the IC for 15 hrs and needed 4 hrs for recharging.
63

Efficient Embedding of Virtual Hypercubes in Irregular WDM Optical Networks

Kithlanagamangala, Guru Prasad P. 14 November 2003 (has links)
This thesis addresses one of the important issues in designing future WDM optical networks. Such networks are expected to employ an all-optical control plane for dissemination of network state information. It has recently been suggested that an efficient control plane will require non-blocking communication infrastructure and routing techniques. However, the irregular nature of most WDM networks does not lend itself to efficient non-blocking communications. It has been recently shown that hypercubes offer some very efficient non-blocking solutions for, all-to-all broadcast operations, which would be very attractive for control plane implementation. Such results can be utilized by embedding virtual structures in the physical network and doing the routing using properties of a virtual architecture. We will emphasize the hypercube due to its proven usefulness. In this thesis we propose three efficient heuristic methods for embedding a virtual hypercube in an irregular host network such that each node in the host network is either a hypercube node or a neighbor of a hypercube node. The latter will be called a satellite or secondary node. These schemes follow a step-by-step procedure for the embedding and for finding the physical path implementation of the virtual links while attempting to optimize certain metrics such as the number of wavelengths on each link and the average length of virtual link mappings. We have designed software that takes the adjacency list of an irregular topology as input and provides the adjacency list of a hypercube embedded in the original network. We executed this software on a number of irregular networks with different connectivities and compared the behavior of each of the three algorithms. The algorithms are compared with respect to their performance in trying to optimize several metrics. We also compare our algorithms to an already existing algorithm in the literature.
64

Design of Power Efficient Multicast Algorithms for Sparse Split WDM Networks

Buddharaju, Kavitha Devi 14 November 2003 (has links)
Recent years witnessed tremendous increase in data traffic as new Internet applications were launched. Optical networks employing recent technologies such as DWDM and EDFA`s emerged as the most prominent and most promising solutions in terms of their ability to keep with the demand on bandwidth. However for a class of applications bandwidth is not the only important requirement, These applications require efficient multicast operations. They include data bases, audio/video conferencing, distributed computing etc. Multicasting in the optical domain however has its own unique set of problems. First, an optical signal can be split among the outputs of a node but the power due to splitting can be significantly reduced. Second, the hardware for split nodes is relatively expensive and therefore we cannot afford to employ it at every node. Third, there are other sources of losses such as attenuation losses and multiplexing /de-multiplexing losses. This thesis deals with the important issue of Power Efficient multicast in WDM optical networks. We report three new algorithms for constructing power efficient multicast trees and forests. Our algorithms are the first to take into account all possible sources of power losses while constructing the trees. We utilize the techniques of backtracking and tree pruning judiciously to achieve very power efficient multicast trees. The first two algorithms use modified versions of the shortest path heuristic to build the tree. The third algorithm however, uses a novel concept and considers power at every tree building step. In this algorithm, the order of inclusion of destination nodes into the tree is based on the power distribution in the tree and not distance. All three algorithms prune the trees if the power levels at the destinations are not acceptable. The performance of these three algorithms under several constraints is studied on several irregular topologies. All three algorithms reported in this work produce significant improvements in signal strength at the set of destinations over the existing multicast algorithms. Numerical results show that our third algorithm outperforms the first two algorithms as well as the existing multicasting algorithms.
65

Computer-Aided Diagnosis Tool for the Detection of Cancerous Nodules in X-Ray Images

Bomma, Pallavi 24 February 2005 (has links)
This thesis involves development of a computer-aided diagnosis (CAD) tool for the detection of cancerous nodules in X-ray images. Both cancerous and non-cancerous regions appear with little distinction on an X-ray image. For accurate detection of cancerous nodules, we need to differentiate the cancerous nodules from the non-cancerous. We developed an artificial neural network to differentiate them. Artificial neural networks (ANN) find a large application in the area of medical imaging. They work in a manner rather similar to the brain and have good decision making criteria when trained appropriately. We trained the neural network by the backpropagation algorithm and tested it with different images from a database of thoracic radiographs (chest X-rays) of dogs from the LSU Veterinary Medical Center. If we give X-ray images directly as input to the ANN, it incurs substantial complexity and training time for the network to process the images. A pre-processing stage involving some image enhancement techniques helps to solve the problem to a certain extent. The CAD tool developed in this thesis works in two stages. We pre-process the digitized images (by contrast enhancement, thresholding, filtering, and blob analysis) obtained after scanning the X-rays and then separate the suspected nodule areas (SNA) from the image by a segmentation process. We then input enhanced SNAs to the backpropagation-trained ANN. When given these enhanced SNAs, the neural network recognition accuracy, compared to unprocessed images as inputs, improved from 70% to 83.33%.
66

Knowledge-Based Fault Detection Using Time-Frequency Analysis

Vongala, Venkata S 24 August 2005 (has links)
This work studies a fault detection method which analyzes sensor data for changes in their characteristics to detect the occurrence of faults in a dynamic system. The test system considered in this research is a Boeing-747 aircraft system and the faults considered are the actuator faults in the aircraft. The method is an alternative to conventional fault detection method and does not rely on analytical mathematical models but acquires knowledge about the system through experiments. In this work, we test the concept that the energy distribution of resolution than the windowed Fourier transform. Verification of the proposed methodology is carried in two parts. The first set of experiments considers entire data as a single window. Results show that the method effectively classifies the indicators by more that 85% as correct detections. The second set of experiments verifies the method for online fault detection. It is observed that the mean detection delay was less than 8 seconds. We also developed a simple graphical user interface to run the online fault detection.
67

IDDQ Testing of a CMOS First Order Sigma-Delta Modulator of an 8-Bit Oversampling ADC

Chamakura, Anand K 02 June 2004 (has links)
This work presents IDDQ testing of a CMOS first order sigma-delta modulator of an 8-bit oversampling analog-to-digital converter using a built-in current sensor [BICS]. Gate-drain, source-drain, gate-source and gate-substrate bridging faults are injected using fault injection transistors. All the four faults cause varying fault currents and are successfully detected by the BICS at a good operation speed. The BICS have a negligible impact on the performance of the modulator and an external pin is provided to completely cut-off the BICS from the modulator. The modulator was designed and fabricated in 1.5 μm n-well CMOS process. The decimator was designed on Altera's FLEXE20K board using Verilog. The modulator and decimator were assembled together to form a sigma-delta ADC.
68

Testing a CMOS Operational Amplifier Circuit Using a Combination of Oscillation and IDDQ Test Methods

Alli, Pavan K 03 June 2004 (has links)
This work presents a case study, which attempts to improve the fault diagnosis and testability of the oscillation testing methodology applied to a typical two-stage CMOS operational amplifier. The proposed test method takes the advantage of good fault coverage through the use of a simple oscillation based test technique, which needs no test signal generation and combines it with quiescent supply current (IDDQ) testing to provide a fault confirmation. A built in current sensor (BICS), which introduces insignificant performance degradation of the circuit-under-test (CUT), has been utilized to monitor the power supply quiescent current changes in the CUT. The testability has also been enhanced in the testing procedure using a simple fault-injection technique. The approach is attractive for its simplicity, robustness and capability of built-in-self test (BIST) implementation. It can also be generalized to the oscillation based test structures of other CMOS analog and mixed-signal integrated circuits. The practical results and simulations confirm the functionality of the proposed test method.
69

Zooplankton Visualization System: Design and Real-Time Lossless Image Compression

Tetala Satya Surya, Dattatreya Reddy 12 July 2004 (has links)
In this thesis, I present a design of a small, self-contained, underwater plankton imaging system. I base the imaging systems design on an embedded PC architecture based on PC/104-Plus standards to meet the compact size and low power requirements. I developed a simple graphical user interface to run on a real-time operating system to control the imaging system. I also address how a real-time image compression scheme implemented on an FPGA chip speeds up image transfer speeds of the imaging system. Since lossless compression of the image is required in order to retain all image details, I began with an established compression scheme like SPIHT, and latter proposed a new compression scheme that suits the imaging systems requirements. I provide an estimate of the total amount of resources required and propose suitable FPGA chips to implement the compression scheme. Finally, I present various parallel designs by which the FPGA chip can be integrated into the imaging system.
70

Design of Optimal Equalizers and Precoders for MIMO Channels

Li, Lijuan 09 July 2003 (has links)
Channel equalization has been extensively studied as a method of combating ISI and ICI for high speed MIMO data communication systems. This dissertation focuses on optimal channel equalization in the presence of non-white observation noises with unknown PSD but bounded power-norm. A worst-case approach to optimal design of channel equalizers leads to an equivalent optimal H-infinity filtering problem for the MIMO communication systems. An explicit design algorithm is derived which not only achieves the zero-forcing (ZF) condition, but also minimizes the RMS error between the transmitted symbols and the received symbols. The second part of this dissertation investigates the design of optimal precoders which minimize the bit error rate (BER) subject to a fixed transmit-power constraint for the multiple antennas downlink communication channels under the perfect reconstruction (PR) condition. The closed form solutions are derived and an efficient design algorithm is proposed. The performance evaluations indicate that the optimal precoder design for multiple antennas communication systems proposed herein is an attractive/reasonable alternative to the existing precoder design techniques.

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