IEEE 802.11 wireless LANs operating in the infrastructure mode are extremely popular and have seen widespread deployment because of their convenience and cost efficiency. A large number of research studies have investigated the performance of DCF, the default MAC protocol in 802.11 WLANs. Previous studies have pointed out several performance problems caused by the interaction of DCF in infrastructure-based WLANs. This thesis addresses a few of these issues. In the first part of the thesis, we address the issue of head-of-line (HOL) blocking at the Access Point (AP) in infrastructure WLANs. We use a cooperative ARQ scheme to resolve the obstruction at the AP queue. We analytically study the performance of our scheme in a single cell IEEE 802.11 infrastructure WLAN under a TCP controlled file download scenario and validate our analysis by extensive simulations. Both analysis and simulation results show considerable increase in system throughput with the cooperative ARQ scheme. We further examine the delay performance of the ARQ scheme in the presence of both elastic TCP traffic and delay sensitive VoIP traffic. Simulations results show that our scheme decreases the delay in the downlink for VoIP packets significantly while simultaneously providing considerable gains in the TCP download throughput. Next, we propose a joint uplink/downlink opportunistic scheduling scheme for maximising system throughput in infrastructure WLANs. We first solve the uplink/downlink unfairness that exists in infrastructure WLANs by maintaining a separate queue and a backoff timer at the AP for each mobile station (STA). We also increase the system throughput by making the backoff timer a function of the channel gains. We analyse the I performance of our scheme under symmetric UDP traffic with i. i. d. channel conditions. Finally, we discuss several opportunistic scheduling policies which aim to increase the system throughput while satisfying certain Quality of Service (QoS) objectives. The standard IEEE 802.11 DCF protocol only offers best-effort services and does not provide any QoS guarantees. Providing QoS in 802.11 networks with time varying channel conditions has proven to be a challenge. We show by simulations that by an appropriate choice of the scheduling metric in our opportunistic scheduling scheme, different QOS objectives like maximizing weighted system sum throughput, minimum rate guarantees and throughput optimality can be attained.

Process variability is a major challenge for the design of nano scale MOSFETs due to fundamental physical limits as well as process control limitations. As the size of the devices is scales down to improve performance, the circuit becomes more sensitive to the process variations. Thus, it is necessary to have a device model that can predict the variations of device characteristics. Statistical modeling method is a potential solution for this problem. The novelty of the work is that we connect BSIM parameters directly to the underlying process parameters. This is very useful for fabs to optimize and control the specific processes to achieve certain circuit metric. This methodology and framework is extendable to any future technologies, because we used a device independent, but process depended frame work In the first part of this thesis, presents the design of nominal MOS devices with 28 nm physical gate length. The device is optimized to meet the specification of low standby power technology specification of International Technology Roadmap for Semiconductors ITRS(2012). Design of experiments are conducted and the following parameters gate length, oxide thickness, halo concentration, anneal temperature and title angle of halo doping are identified as the critical process parameters. The device performance factors saturation current, sub threshold current, output impendence and transconductance are examined under process variabilty. In the subsequent sections of the thesis, BSIM parameter extraction of MOS devices using the software ICCAP is presented. The variability of the spice parameters due to process variation is extracted. Using the extracted data a new BSIM interpolated model for a variability aware circuit design is proposed assume a single process parameter is varying. The model validation is done and error in ICCAP extraction method for process variability is less than 10% for all process variation condition in 3σ range. In the next section, proposes LUT model and interpolated method for a variability aware circuit design for single parameter variation. The error in LUT method for process variability reports less than 3% for all process variation condition in 3σ range. The error in perdition of drain current and intrinsic gain for LUT model files are very close to the result of device simulation. The focus of the work was to established effective method to interlink process and SPICE parameters under variability. This required generating a large number of BSIM parameter ducks. Since there could be some inaccuracy in large set of BSIM parameters, we used LUT as a golden standard. We used LUT modeling as a benchmark for validation of our BSIM3 model In the final section of thesis, impact of multi parameter variation of the processes in device performance is modelled using RSM method; the model is verified using ANOVA method. Models are found to be sufficient and stable. The reported error is less than 1% in all cases. Monte Carlo simulation confirms stability and repeatability of the model. The model for random variabilty of process parameters are formulated using BSIM and compared with the LUT model. The model was tested using a benchmark circuit. The maximum error in Monte Carlo simulation is found to be less than 3% for output current and less than 8% for output impedance.

MEMS Sensors are widely used for sensing inertial displacements. The displacements arising out of acceleration /Coriolis effect are typically in the range of 1 nm-1 m. This work investigates the realization of high resolution MEMS inertial sensors using novel displacement sensing mechanisms. Capacitance sensing ASIC is developed as part of conventional electronics interface with MEMS sensor under the conventional CMOS-MEMS integration strategy. The capacitance sense ASIC based on Continuous Time Voltage scheme with coherent and non-coherent demodulation is prototyped on AMS 0.35 m technology. The ASIC was tested to sense C = 3.125 fF over a base of 2 pF using on-chip built-in test capacitors. Dynamic performance of this ASIC was validated by interfacing with a DaCM MEMS accelerometer. 200milli-g of acceleration (equivalent to a C = 2.8 fF) over an input frequency of 20Hz is measurable using the developed ASIC. The observed sensitivity is 90mV/g. The ASIC has several programmable features such as variation in trim capacitance (3.125 fF-12.5 pF), bandwidth selection (500 Hz-20 kHz) and variable gain options (2-100). Capacitance detection, a dominant sensing principle in MEMs sensors, experiences inherent limitation due to the role of parasitics when the displacements of interest are below 5 nm range. The capacitive equivalence ( C) for the range of displacements of the order of 5 nm and below would vary in the range atto-to-zepto farad. Hence there is a need to explore alternative sensing schemes which preferably yield higher sensitivity (than those offered by the conventional integration schemes) and are based on the principle of built-in transduction to help overcome the influence of parasitics on sensitivity. In this regard, 3 non-conventional architectures are explored which fall under the direct integration classification namely: (a) Sub-threshold based sensing (b) Fringe field based sensing and (c) Tunneling current based sensing. a) In Sub-threshold based sensing, FET with a suspended gate is used for displacement sensing. The FET is biased in the sub-threshold region of operation. The exponential modulation of drain current for a change in displacement of 1 nm is evaluated using TCAD, and the in uence of initial air-gap variation on the sensitivity factor ( ID=ID) is brought out. For 1% change in air gap displacement (i.e., TGap/TGap, the gap variation resulting due to the inertial force / mass loading) nearly 1050% change in drain current( ID=ID) is observed (considering initial air gaps of the order 100 nm). This validates the high sensitivity offered by the device in this regime of operation. A comparison of sensitivity estimate using the capacitive equivalence model and TCAD simulated model for different initial air-gaps in a FD-SOI FET is brought out. The influence of FDSOI FET device parameters on sensitivity, namely the variation of TSi, TBox, NA and TGap are explored. CMOS compatibility and fabrication feasibility of this architecture was looked into by resorting to the post processing approach used for validating the sub-threshold bias concept. The IMD layers of the Bulk FETs fabricated through AMS 0.35 technology were etched using BHF and IPA mixture to result in a free standing metal (Al) layers acting as the suspended gate. The performance estimate is carried out considering specific Equivalent Gap Thickness (EGT) of 573 nm and 235 nm, to help overcome the role of coupled electrostatics in influencing the sensitivity metric. The sensitivity observed by biasing this post processed bulk FET in sub-threshold is 114% ( ID=ID change) for a 59% ( d/d change). The equivalent C in this case is 370 aF. b) In Fringe eld based sensing approach, a JunctionLess FET (JLFET) is used as a depletion mode device and an out-of-plane gate displacement would help modulate the device pinch-o voltage due to fringe field coupling. The resulting change in the gate fringe field due to this displacement modulates the drain current of the JunctionLess FET. The displacement induced fringe field change (relative to the FET channel) brings about a distinct shift in the ID-VG characteristics of the JLFET. For displacement d = 2 nm, the JLFET with a channel doping of ND = 8X1018cm 3 and a bias point of VG = -47.7 V, 98% enhancement in sensitivity is observed in 3D TCAD simulations. The equivalent C in this case is 29 zF. The role of ground-planes in the device operation is explored. c) In the tunneling current based sensing approach, the beams fabricated using the SOI-MUMPS process are FIB milled so as to create very ne air gaps of the order of nearly 85 nm. Under high electric fields of the order > 8 MV/cm, the lateral displacement based tunneling sensor offers enhanced change in sensitivity for an induced external force at a fixed DC bias. When integrated as an array with varying electrode overlap, this technique can track displacements over a wide range. With the initial beam overlap as 1.2 m, for a lateral displacement of 1.2 m, a 100% change in sensitivity ( ID=ID) is observed. The effect of fringe field can be completely neglected here unlike its capacitive beam equivalent.