This thesis is devoted to the fabrication of carbon nanotube structures for microelectronics packaging applications with an emphasis on fundamental studies of nanotube growth and assembly, wetting of nanotube structures, and nanotube-based composites. A CVD process is developed that allows controlled growth of a variety of CNT structures, such as CNT films, bundles, and stacks. Use of an Al2O3 support enhances the Fe catalyst activity by increasing the CNT growth rate by nearly two orders of magnitude under the same growth conditions. By introducing a trace amount of weak oxidants into the CVD chamber during CNT growth, aligned CNT ends can be opened and/or functionalized, depending on the selection of oxidants. By varying the growth temperature, CNT growth can be performed in a gas diffusion- or kinetics-controlled regime. To overcome the challenges that impede implementation of CNTs in circuitry, a CNT transfer process was proposed to assemble aligned CNT structures (films, stacks &bundles) at low temperature which ensures compatibility with current microelectronics fabrication sequences and technology. Field emission and electrical testing of the as-assembled CNT devices indicate good electrical contact between CNTs and solder and a very low contact resistance across CNT/solder interfaces. For attachment of CNTs and other applications (e.g. composites), wetting of nanotube structures was studied. Two model surfaces with two-tier scale roughness were fabricated by controlled growth of CNT arrays followed by coating with fluorocarbon layers formed by plasma polymerization to study roughness geometric effects on superhydrophobicity. Due to the hydrophobicity of nanotube structures, electrowetting was investigated to reduce the hydrophobicity of aligned CNTs by controllably reducing the interfacial tension between carbon nanotubes (CNTs) and liquids. Electrowetting can greatly reduce the contact angle of liquids on the surfaces of aligned CNT films. However, contact angle saturation still occurs. Variable frequency microwave (VFM) radiation can greatly improve the CNT/epoxy interfacial bonding strength. Compared to composites cured by thermal heating, VFM-cured composites demonstrate higher CNT/matrix interfacial bonding strength, which is reflected in composite negative thermal expansion. The improved CNT/epoxy interface enhances the thermal conductivity of the composites by 26-30%.

Inter-chip input-output (I/O) communication bandwidth demand, which rapidly scaled with integrated circuit scaling, has leveraged equalization techniques to operate reliably on band-limited channels at additional power and area complexity. High-bandwidth inter-chip optical interconnect architectures have the potential to address this increasing I/O bandwidth. Considering future tera-scale systems, power dissipation of the high-speed I/O link becomes a significant concern. This work presents a design flow for the power optimization and comparison of high-speed electrical and optical links at a given data rate and channel type in 90 nm and 45 nm CMOS technologies. The electrical I/O design framework combines statistical link analysis techniques, which are used to determine the link margins at a given bit-error rate (BER), with circuit power estimates based on normalized transistor parameters extracted with a constant current density methodology to predict the power-optimum equalization architecture, circuit style, and transmit swing at a given data rate and process node for three different channels. The transmitter output swing is scaled to operate the link at optimal power efficiency. Under consideration for optical links are a near-term architecture consisting of discrete vertical-cavity surface-emitting lasers (VCSEL) with p-i-n photodetectors (PD) and three long-term integrated photonic architectures that use waveguide metal-semiconductor-metal (MSM) photodetectors and either electro-absorption modulator (EAM), ring resonator modulator (RRM), or Mach-Zehnder modulator (MZM) sources. The normalized transistor parameters are applied to jointly optimize the transmitter and receiver circuitry to minimize total optical link power dissipation for a specified data rate and process technology at a given BER. Analysis results shows that low loss channel characteristics and minimal circuit complexity, together with scaling of transmitter output swing, allows electrical links to achieve excellent power efficiency at high data rates. While the high-loss channel is primarily limited by severe frequency dependent losses to 12 Gb/s, the critical timing path of the first tap of the decision feedback equalizer (DFE) limits the operation of low-loss channels above 20 Gb/s. Among the optical links, the VCSEL-based link is limited by its bandwidth and maximum power levels to a data rate of 24 Gb/s whereas EAM and RRM are both attractive integrated photonic technologies capable of scaling data rates past 30 Gb/s achieving excellent power efficiency in the 45 nm node and are primarily limited by coupling and device insertion losses. While MZM offers robust operation due to its wide optical bandwidth, significant improvements in power efficiency must be achieved to become applicable for high density applications.