Thesis (M.S.)--University of Texas at El Paso, 2009. / Title from title screen. Vita. CD-ROM. Includes bibliographical references. Also available online.

Thesis (M.Phil.) - University of Queensland, 2004. / Includes bibliography.

Thesis (MScEng)--University of Stellenbosch, 2004. / ENGLISH ABSTRACT: Flash memory and the errors induced in it by radiation were studied. A test board was then designed and developed as well as a radiation test program. The system was irradiated. This gave successful results, which confirmed aspects of the study and gave valuable insight into flash memory behaviour. To date, the board is still being used to test various flash devices for radiation-harsh environments. A memory protection unit (MPU) was conceptually designed and developed to morntor flash devices, increasing their reliability in radiation-harsh environments. This unit was designed for intended use onboard a micro-satellite. The chosen flash device for this study was the K9F1208XOA model from SAMSUNG. The MPU was designed to detect, maintain, mitigate and report radiation induced errors in this flash device. Most of the design was implemented in field programmable gate arrays and was realised using VHDL. Simulations were performed to verify the functionality of the design subsystems. These simulations showed that the various emulated errors were handled successfully by the MPU. A modular design methodology was followed, therefore allowing the chosen flash device to be replaced with any flash device, following a small reconfiguration. This also allows parts of the system to be duplicated to protect more than one device. / AFRIKAANSE OPSOMMING: 'n Studie is gemaak van" Flash" geheue en die foute daarop wat deur radiasie veroorsaak word. 'n Toetsbord is ontwerp en ontwikkel asook 'n radiasie toetsprogram waarna die stelsel bestraal is. Die resultate was suksesvol en het aspekte van die studie bevestig en belangrike insig gegee ten opsigte van "flash" komponente in radiasie intensiewe omgewmgs. 'n Geheue Beskermings Eenheid (GBE) is konseptueel ontwerp en ontwikkelom die "flash" komponente te monitor. Dit verhoog die betroubaarheid in radiasie intensiewe omgewings. Die eenheid was ontwerp met die oog om dit aan boord 'n mikro-satelliet te gebruik. Die gekose "flash" komponent vir die studie was die K9F1208XOA model van SAMSUNG. Die GBE is ontwerp om foute wat deur radiasie geïnduseer word in die "flash" komponent te identifiseer, herstel en reg te maak. Die grootste deel van die implementasie is gedoen in "field programmable gate arrays" and is gerealiseer deur gebruik te maak van VHDL. Simulasies is gedoen om die funksionaliteit van die ontwikkelde substelsels te verifieer. Hierdie simulasies het getoon dat die verskeie geëmuleerde foute suksesvol deur die GBE hanteer is. 'n Modulre ontwerpsmetodologie is gevolg sodat die gekose "flash" komponent deur enige ander flash komponent vervang kan word na gelang van 'n eenvoudige herkonfigurasie. Dit stelook dele van die sisteem in staat om gedupliseer te word om sodoende meer as een komponent te beskerm.

Thesis (MScEng)--University of Stellenbosch, 2002. / ENGLISH ABSTRACT: This thesis presents the design and implementation of a voltage controller for an Uninterruptible Power Supply (UPS) Inverter. The inverter is capable of producing a nearly sinusoidal output voltage waveform, thereby keeping the Total Harmonic Distortion (THD) to a minimum. Digital controllers introduce a time delay in the control law that causes system instability. Various control techniques, which includes Pade approximations and system augmentation, are investigated to eliminate the effect of the time delay. These controllers employ classical control as well as modem control techniques. The selection of the various control parameters is verified by mathematical equations. A load-disturbance compensation scheme, implementing feed-forward and gain scheduling, is also developed to improve voltage distortion when varying loads, such as non-linear loads, are connected to the system. It is shown that the constructed pulse-width modulated (PWM) control scheme can achieve fast dynamic response as well as a low THD. / AFRIKAANSE OPSOMMING: Hierdie verhandeling ondersoek die ontwerp en implementering van 'n spanningsbeheerder vir 'n ononderbroke kragtoevoer omsetter. Die stelsel produseer 'n uittree spannigsgolfvorm met 'n lae Totale Harmoniese Distorisie (THD). Digital beheerders veroorsaak 'n tydvertraging in die beheerwet wat stelsel onstabiliteit kan veroorsaak. Verskeie beheertegnieke wat gebaseer is op die Pade benaderings van die tydvertraging en stelsel aanpassings, is ondersoek. Hierdie beheerders maak gebruik van klassieke en moderne beheertegnieke. Die seleksie van die verskeie beheerderveranderlikes word gestaaf deur wiskundige vergelykings. Spannigsvervorming word tot 'n minimum beperk deur gebruik te maak van 'n lasveranderings-kompensasietegniek wat onderskeidelik vorentoe-voer en aanwins skedulering implementeer. Verder word daar bewys dat die pulswydte modulasie (PWM) beheerskema vinnige dinamiese gedrag asook 'n lae THD bewerkstellig.

Orientador: Jose Antenor Pomilio / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-13T08:24:07Z (GMT). No. of bitstreams: 1 Ortenzi_Gustavo_M.pdf: 4885292 bytes, checksum: 8a23d8845eaad19c72fe6f84e13af963 (MD5) Previous issue date: 2009 / Resumo: Descreve-se neste trabalho o desenvolvimento de uma fonte de alimentação chaveada para utilização em eletrodomésticos, capaz de entregar três saídas com níveis de tensão e potência diferentes, com uma mínima troca de componentes entre as três versões. Na primeira parte do trabalho é apresentada a aplicação da fonte e suas necessidades, seguido das especificações e da escolha da topologia e do modo de operação. Dando continuidade no desenvolvimento do projeto da fonte, apresenta-se a metodologia de cálculo adotada para o dimensionamento dos componentes a serem utilizados. Uma vez com os componentes dimensionados, apresenta-se a seleção dos componentes visando a estratégia de escalabilidade. Finalizando o dimensionamento dos componentes, apresenta-se o esquemático da fonte de alimentação e os componentes que são modificados de acordo com a versão em questão. A seguir, apresentam-se os resultados obtidos dos testes de regulação cruzada das saídas, as principais formas de onda de corrente e tensão do conversor, o rendimento das três versões considerando diferentes tensões de entrada de rede e a resposta a transiente. Fechando os resultados práticos, apresentam-se os ensaios de desenvolvimento de EMC/EMI, mostrando os resultados iniciais, as modificações implementadas e as soluções adotadas. No último capítulo apresenta-se as conclusões e as perspectivas de continuidade de desenvolvimento deste trabalho. / Abstract: This work describes the development of a switch mode power supply to be used at home appliances, capable to deliver three outputs with voltage and power different levels, changing a minimum number of components between them. At the first part of the work is presented the application of the power supply and its needs, followed by the specifications and choose of the topology and the operation mode. Continuing the design of the power supply's project, it is presented the methodology adopted to calculate and select the components to be used. With the components selected, it is presented the components selection criteria looking the scalability strategy. Ending the component's calculation and selection, the power supply schematic and the components that change according to the used version are shown. After the design, experimental results of the output cross regulation, main waveforms of voltage and current, efficiency and transient response of the three versions considering different AC Mains voltages are shown. Closing the experimental results, the EMI/EMC tests are presented, presenting the preliminary results, followed by the adopted modifications and solutions. The last chapter presents the conclusions and the perspectives of new developments of this work. / Mestrado / Energia Eletrica / Mestre em Engenharia Elétrica

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 1981. / Includes bibliographical references. / by Samuel Franklin Horton. / Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 1981.

In the face of increasing awareness among customers and today's competitive market, the warranty of a product has become an added feature in marketing strategy. A reliable product causes less warranty support cost. However, a more reliable product costs more to manufacture. Thus, a suitable trade-off between the cost and the benefit of a development and testing program is essential to optimize the performance measure, e. g., minimize total expected cost. Renewal theoretic models of sequences of failures over the burn-in and warranty periods and their costs are developed. Contrary to the usual asymptotic assumptions, transient behaviors of the renewal processes are considered. The expected costs associated with in-plant and field failures are balanced against the costs of implementing a burn-in program. A multi-component series system with different Weibull distributions for the components are considered. Burn-in is performed at the assembly level and the components are assumed to have different age accelerations under a common stress regimen. Models based on analyses both at the component and the system level are constructed. Two different burn-in policies are considered. These are "fixed duration" bum-in and "failure freell burn-in. A free replacement warranty for the components with policies of both fixed warranty period and renewed warranty period after each failure is considered in the models. The profit functions under different models are optimized with respect to burn-in period, stress parameters and warranty period. The models are extended to include reliability growth over the warranty period. Finally I solution procedures for optimizing the profit functions for all cases are given. / Ph. D.

One of the main challenges in the electronics manufacturing and packaging development is how to integrate more functions inside the same or even smaller size. To meet the demand for higher integration, the interest toward passive and active component embedding has been increasing during the past few years. One of the main reasons for the growing interest toward embedded active components, in addition to demand for higher packaging density, is the need for better electrical performance of the component assemblies. However, it is little known how embedded IC and passives affect the reliability of IC packaging. Solder joints have been used in the electronic industry as both structural and electrical interconnections between electronic packages and printed circuit boards (PCB). When solder joints are under thermal cyclic loading, mismatch in coefficients of thermal expansion (CTE) between the printed circuit boards and the solder balls creates thermal strains and stresses on the joints, which may finally result in cracking. Consequently, the mechanical interconnection is lost, leading to electrical failures (such as hard/intermittent open, parametric failure), which in turn causes malfunction of the circuit or whole system. When a die is embedded into a substrate, Young's modulus of the die is larger than one of the core of the substrate and the CTEs of the die is smaller than those of the substrate. As a result, mismatch in coefficients of thermal expansions (CTE) between the substrate with the embedded device and the solder balls may increase. In the present study, the stress of chip scale packages (CSP) with an embedded die under thermal cycling conditions is evaluated using the finite element method. The viscoplastic model for solders including matrix dislocation mechanism and grain boundary sliding model developed by Yi et al. (2002) is employed.

Post-silicon validation has become a critical stage in the system-on-chip (SoC) development cycle, driven by increasing design complexity, higher level of integration and decreasing time-to-market. According to recent reports, post-silicon validation effort comprises more than 50% of the overall development effort of an 65nm SoC. Though post-silicon validation covers many aspects ranging from electronic properties of hardware to performance and power consumption of whole systems, a central task remains validating functional correctness of both hardware and its integration with software. There are several key challenges to achieving accelerated and low-cost post-silicon functional validation. First, there is only limited silicon observability and controllability; second, there is no good test coverage estimation over a silicon device; third, it is difficult to generate good post-silicon tests before a silicon device is available; fourth, there is no effective software robustness testing approaches to ensure the quality of hardware/software integration. We propose a systematic approach to accelerating post-silicon functional validation with virtual prototypes. Post-silicon test coverage is estimated in the pre-silicon stage by evaluating the test cases on the virtual prototypes. Such analysis is first conducted on the initial test suite assembled by the user and subsequently on the expanded test suite which includes test cases that are automatically generated. Based on the coverage statistics of the initial test suite on the virtual prototypes, test cases are automatically generated to improve the test coverage. In the post-silicon stage, our approach supports coverage evaluation of test cases on silicon devices to ensure fidelity of early coverage evaluation. The generated test cases are issued to silicon devices to detect inconsistencies between virtual prototypes and silicon devices using conformance checking. We further extend the test case generation framework to generate and inject fault scenario with virtual prototypes for driver robustness testing. Besides virtual prototype-based fault injection, an automatic driver fault injection approach is developed to support runtime fault generation and injection for driver robustness testing. Since virtual prototype enables early driver development, our automatic driver fault injection approach can be applied to driver testing in both pre-silicon and post-silicon stages. For preliminary evaluation, we have applied our coverage evaluation and test generation to several network adapters and their virtual prototypes. We have conducted coverage analysis for a suite of common tests on both the virtual prototypes and silicon devices. The results show that our approach can estimate the test coverage with high fidelity. Based on the coverage estimation, we have employed our automatic test generation approach to generate additional tests. When the generated test cases were issued to both virtual prototypes and silicon devices, we observed significant coverage improvement. And we detected 20 inconsistencies between virtual prototypes and silicon devices, each of which reveals a virtual prototype or silicon device defect. After we applied virtual prototype-based fault injection approach to virtual prototypes for three widely-used network adapters, we generated and injected thousands of fault scenarios and found 2 driver bugs. For automatic driver fault injection, we have applied our approach to 12 widely used drivers with either virtual prototypes or silicon devices. After testing all these drivers, we found 28 distinct bugs.

Advances in electronics fabrication, coupled with the demand for increased computing power, have driven the demand for innovative cooling solutions to dissipate waste heat generated by these devices. To meet future demands, research and development has focused on robust and stable two-phase heat transfer devices. A confined impinging jet is explored as means of utilizing two-phase heat transfer while minimizing flow instabilities observed in microchannel devices. The test configuration consists of a 4 mm diameter jet of water that impinges on a 38 mm diameter heated aluminum surface. Experimental parameters include inlet mass flow rates from 150 to 600 g/min, nozzle-to-surface spacing from 1 to 8 mm, and input heat fluxes from 0 to 90 W/cm2. Results were used to assess the influence of the testing parameters on the heat transfer performance and stability characteristics of a two-phase confined impinging jet. Stability characteristics were explored using power spectral densities (PSDs) of the inlet pressure time series data. Confined impinging jets, over the range of conditions tested, were found to be stable and an efficient means of removing large amounts of waste heat. The radial geometry of the confined jet allows the fluid to expand as it flows radially away from the nozzle, which suppresses instabilities found in microchannel array geometries. Conditions of the heater surface were found to strongly influence two-phase performance. Analysis of PSDs, for stable operation, showed dominate frequencies in the range of 1-4 Hz, which were attributed to generated vapor expanding in the outlet plenum and the subsequent collapse as it condensed. A stability indicator was developed by inducing artificial instabilities into the system by varying the amount of cross sectional area available for outlet vapor removal and compared to the results for stable operation. / Graduation date: 2012