Advances in VLSI manufacturing and design technology over the decades have created many computing paradigms for disparate computing needs. With concerns for transmission cost, security, latency of centralized computing, edge/local computing are increasingly prevalent in the faster growing sectors like Internet-of-Things (IoT) and other sectors that require energy/connectivity autonomous systems such as biomedical and industrial applications. Energy and power efficient are the main design constraints in local and edge computing. While there exists a wide range of low power design techniques, they are often underutilized in custom circuit designs as the algorithms are developed independent of the hardware. Such compartmentalized design approach fails to take advantage of the many compatible algorithmic and hardware techniques that can improve the efficiency of the entire system. Algorithm hardware co-design is to explore the design space with whole stack awareness. The main goal of the algorithm hardware co-design methodology is the enablement and improvement of small form factor edge and local VLSI systems operating under strict constraints of area and energy efficiency. This thesis presents selected works of application specific digital and mixed-signal integrated circuit designs. The application space ranges from implantable biomedical devices to edge machine learning acceleration.

The capability of measuring surface temperatures of hybrid circuits at the Virginia Tech Hybrid Microelectronics Laboratory has been established. This capability provides a quantitative method for effectively evaluating thermal design software. Surface operating temperatures were measured and predicted for an operating hybrid circuit. The temperatures were measured using an infrared thermal imaging system, which measures surface temperatures by detecting the infrared radiation emitted and reflected. The accuracy of the measurements has been quantified for variations in surface emissivity, convective cooling condition, and operating temperature range. The most accurate temperature measurement of a one-resistor circuit was compared to the operating temperature predicted by a lumped-parameter one-dimensional heat transfer analysis. The comparison agreed within the expected limits for this simple analysis and identified areas for possible improvement both of the model and the experimental technique. Thermal design of a circuit is critical because excessive temperatures are a common cause of circuit failure. Circuit designers rely on computer programs to predict circuit component temperatures because of the high cost of prototype experimentation. Accurate thermal design software that is currently available is too complicated for occasional use by circuit designers. Simple, yet accurate, thermal design software is essential for this type of design, so that circuit layouts can be quickly and easily optimized. / M.S.

Thesis (PhD (Electric and Electronic Engineering))--University of Stellenbosch, 2007. / There is increasing use of commercial components in space technology and it is important to recognize that the space radiation environment poses the risk of permanent malfunction due to radiation. Therefore, the integrated circuits used for spacecraft electronics must be resistant to radiation. The effect of using the MOSFET device in a radiation environment is that the gate oxide becomes ionized by the dose it absorbs due to the radiation induced trapped charges in the gate-oxide. The trapped charges in the gate-oxide generate additional space charge fields at the oxide-substrate interface. After a sufficient dose, a large positive charge builds up, having the same effect as if a positive voltage was applied to the gate terminal. Therefore, the transistor source to drain current can no longer be controlled by the gate terminal and the device remains on permanently resulting in device failure. There are four processes involved in the radiation response of MOS devices. First, the ionizing radiation acts with the gate oxide layer to produce electron-hole pairs. Some fraction of the electron-hole pairs recombine depending on the type of incident particle and the applied gate to substrate voltage, i.e. the electric field. The mobility of the electron is orders of magnitude larger than that of the holes in the gate oxide, and is swept away very quickly in the direction of the gate terminal. The time for the electrons to be swept away is on the order of 1ps. The holes that escape recombination remain near their point of origin. The number of these surviving holes determines the initial response of the device after a short pulse of radiation. The cause of the first process, i.e. the presence of the electric field, is the main motivation for design method described in this dissertation. The second process is the slow transport of holes toward the oxide-silicon interface due to the presence of the electric field. When the holes reach the interface, process 3, they become captured in long term trapping sites and this is the main cause of the permanent threshold voltage shift in MOS devices. The fourth process is the buildup of interface states in the substrate near the interface The main contribution of this dissertation is the development of the novel Switched Modular Redundancy (SMR) method for mitigating the effects of space radiation on satellite electronics. The overall idea of the SMR method is as follows: A charged particle is accelerated in the presence of an electric field. However, in a solid, electrons will move around randomly in the absence of an applied electric field. Therefore if one averages the movement over time there will be no overall motion of charge carriers in any particular direction. On applying an electric field charge carriers will on average move in a direction aligned with the electric field, with positive charge carriers such as holes moving in the direction of field, and negative charge carriers moving in the opposite direction. As is the case with process one and two above. It is proposed in this dissertation that if we apply the flatband voltage (normaly a zero bias for the ideal NMOS transistor) to the gate terminal of a MOS transistor in the presence of ionizing radiation, i.e. no electric field across the gate oxide, both the free electrons and holes will on average remain near their point of origin, and therefore have a greater probability of recombination. Thus, the threshold voltage shift in MOS devices will be less severe for the gate terminal in an unbiased condition. The flatband conditions for the real MOS transistor is discussed in appendix E. It was further proposed that by adding redundancy and applying a resting policy, one can significantly prolong the useful life of MOS components in space. The fact that the rate of the threshold voltage shift in MOS devices is dependant on the bias voltage applied to the gate terminal is a very important phenomenon that can be exploited, since we have direct control and access to the voltage applied to the gate terminal. If for example, two identical gates were under the influence of radiation and the gate voltage is alternated between the two, then the two gates should be able to withstand more total dose radiation than using only one gate. This redundancy could be used in a circuit to mitigate for total ionizing dose. The SMR methodology would be to duplicate each gate in a circuit, then selectively only activating one gate at a time allowing the other to anneal during its off cycle. The SMR algorithm was code in the “C” language. In the proposed design methodology, the design engineer need not be concerned about radiation effects when describing the hardware implementation in a hardware description language. Instead, the design engineer makes use of conventional design techniques. When the design is complete, it is synthesized to obtain the gate level netlist in edif format. The edif netlist is converted to structural VHDL code during synthesis. The structural VHDL netlist is fed into the SMR “C” algorithm to obtain the identical redundant circuit components. The resultant file is also a structural VHDL netlist. The generated VHDL netlist or SMR circuit can then be mapped to a Field Programmable Gate Array (FPGA). Spacecraft electronic designers increasingly demand high performance microprocessors and FPGAs, because of their high performance and flexibility. Because FPGAs are reprogrammable, they offer the additional benefits of allowing on-orbit design changes. Data can be sent after launch to correct errors or to improve system performance. System including FPGAs covers a wide range of space applications, and consequently, they are the object of this study in order to implement and test the SMR algorithm. We apply the principles of reconfigurable computing to implement the Switched Modular Redundancy Algorithm in order to mitigate for Total Ionizing Dose (TID) effects in FPGA’s. It is shown by means of experimentation that this new design technique provides greatly improved TID tolerance for FPGAs. This study was necessary in order to make the cost of satellite manufacturing as low as possible by making use of Commercial off-the-shelf (COTS) components. However, these COTS components are very susceptible to the hazards of the space environment. One could also make use of Radiation Hard components for the purpose of satellite manufacturing, however, this will defeat the purpose of making the satellite manufacturing cost as low as possible as the cost of the radiation hard electronic components are significantly higher than their commercial counterparts. Added to this is the undesirable fact that the radiation hard components are a few generations behind as far as speed and performance is concerned, thus providing even greater motivation for making use of Commercial components. Radiation hardened components are obtained by making use of special processing methods in order to improve the components radiation tolerance. Modifying the process steps is one of the three ways to improve the radiation tolerance of an integrated circuit. The two other possibilities are to use special layout techniques or special circuit and system architectures. Another method, in which to make Complementary Metal Oxide Silicon (CMOS) circuits tolerant to ionizing radiation is to distribute the workload among redundant modules (called Switched Modular Redundancy above) in the circuit. This new method will be described in detail in this thesis.

No description available.

Cellular and mobile communication markets, together with CMOS technology scaling, have made complex systems-on-chip integrated circuits (ICs) ubiquitous. Moving towards the internet of things that aims to extend this further requires ultra-low power and efficient radio communication that continues to take advantage of nanoscale CMOS processes. At the heart of this lie orthogonal challenges in both system and circuit architectures of current day technology. By enabling transceivers at center frequencies ranging in several tens of GHz, modern CMOS processes support bandwidths of up to several GHz. However, conventional narrowband architectures cannot directly translate or trade-off these speeds to lower power consumption. Pulse-radio UWB (PR-UWB), a fundamentally different system of communication enables this trade-off by bit-level duty-cycling i.e., power-gating and has emerged as an alternative to conventional narrowband systems to achieve better energy efficiency. However, system-level challenges in the implementation of transceiver synchronization and duty-cycling have remained an open challenge to realize the ultra-low power numbers that PR-UWB promises. Orthogonally, as CMOS scaling continues, approaching 28nm and 14nm in production digital processes, the key transistor characteristics have rapidly changed. Changes in supply voltage, intrinsic gain and switching speeds have rendered conventional analog circuit design techniques obsolete, since they do not scale well with the digital backend engines that dictate scaling. Consequently, circuit architectures that employ time-domain processing and leverage the faster switching speeds have become attractive. However, they are fundamentally limited by their inability to support linear domain-to-domain conversion and hence, have remained un-suited to high-performance applications. Addressing these requirements in different dimensions, two pulse-radio UWB receiver and a continuous-time filter silicon prototypes are presented in this work. The receiver prototypes focus on system level innovation while the filter serves as a demonstration vehicle for novel circuit architectures developed in this work. The PR-UWB receiver prototypes are implemented in a 65nm LP CMOS technology and are fully integrated solutions. The first receiver prototype is a compact UWB receiver front end operating at 4.85GHz that is aggressively duty-cycled. It occupies an active area of only 0.4 mm², thanks to the use of few inductors and RF G_m-C filters and incorporates an automatic-threshold-recovery-based demodulator for digitization. The prototype achieves a sensitivity of -88dBm at a data rate of 1Mbps (for a BER of 10^-3), while achieving the lowest energy consumption gradient (dP/df_data=450pJ/bit) amongst other receivers operating in the lower UWB band, for the same sensitivity. However, this prototype is limited by idle-time power consumption (e.g., bias) and lacks synchronization capability. A fully self-duty-cycled and synchronized UWB pulse-radio receiver SoC targeted at low-data-rate communication is presented as the second prototype. The proposed architecture builds on the automatic-threshold-recovery-based demodulator to achieve synchronization using an all-digital clock and data recovery loop. The SoC synchronizes with the incoming pulse stream from the transmitter and duty-cycles itself. The SoC prototype achieves a -79.5dBm, 1Mbps-normalized sensitivity for a >5X improvement over the state of the art in power consumption (375pJ/bit), thanks to aggressive signal path and bias circuit duty-cycling. The SoC is fully integrated to achieve RF-in to bit-out operation and can interface with off-chip, low speed digital components. Finally, switched-mode signal processing, a signal processing paradigm that enables the design of highly linear, power-efficient feedback amplifiers is presented. A 0.6V continuous-time filter prototype that demonstrates the advantages of this technique is presented in a 65nm GP CMOS process. The filter draws 26.2mW from the supply while operating at a full-scale that is 73% of the V_dd, a bandwidth of 70MHz and a peak signal-to-noise-and-distortion ratio (SNDR) of 55.8dB. This represents a 2-fold improvement in full-scale and a 10-fold improvement in the bandwidth over state-of-the-art filter implementations, while demonstrating excellent linearity and signal-to-noise ratio. To sum up, innovations spanning both system and circuit architectures that leverage the speeds of nanoscale CMOS processes to enable power-efficient solutions to next-generation wireless receivers are presented in this work.

Delta-Sigma Modulator-based Analog-to-Digital converter design is an active area of research. New topologies require extensive simulations to verify their performance. A series of improvements were made to an existing circuit simulation package in order to speed the simulation process for the designer. Various examples of these improvements are presented in typical applications. / Graduation date: 1992

No description available.

Thesis (M.S.) -- Mississippi State University. Department of Electrical and Computer Engineering. / Title from title screen. Includes bibliographical references.

Orientador: Carlos Alberto dos Reis Filho / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e Computação / Made available in DSpace on 2018-08-05T22:28:31Z (GMT). No. of bitstreams: 1 ManzanJunior_Donato_M.pdf: 1716370 bytes, checksum: 70e88e04a73f17039cb0ea8597b7b0cc (MD5) Previous issue date: 2005 / Resumo: Este trabalho descreve o desenvolvimento de um sensor de umidade relativa que tem como elemento sensor um polímero (poli(óxido de etileno-co-epicloridrina)84:16), cuja condutividade varia com a umidade. O polímero foi depositado por casting sobre um substrato cerâmico sobre o qual, por sua vez, foram depositados dois eletrodos em forma interdigitada aos quais é aplicada uma corrente alternada com forma de onda quadrada e amplitude DC nula. Este sinal de excitação é produzido por um circuito integrado que também realiza a leitura da tensão nos terminais do eletrodo. Além disto, o circuito contém um sensor de temperatura cuja informação é necessária para a correta leitura da umidade. Amostras do circuito integrado, cujo projeto é parte deste trabalho, foram fabricadas em tecnologia CMOS 0,35um e caracterizadas juntamente com o elemento sensor. Os resultados mais relevantes da caracterização do sensor desenvolvido são: Faixa de medição: máx 90%RH para evitar condensação; Sensibilidade do elemento sensor: 188,83W/%RH a 55%RH; Histerese: 3,4% a 55%RH; Temperatura de operação: 0 a 60oC; Tempo de resposta: +/-30s. A principal contribuição deste trabalho reside na proposição de um sensor de umidade que é composto de um elemento sensor polimérico e de um circuito integrado que realiza o condicionamento e leitura dos sinais envolvidos, constituindo deste modo uma solução robusta e de baixo custo / Abstract: This work describes the development of a relative-humidity sensor, which uses as sensing element a polymer (poly(ethylene oxide-co-epichlorohydrin)84:16) whose conductivity varies with humidity. The polymer was deposited by casting over a ceramic substrate, on which two interdigitized electrodes were previously deposited. An integrated circuit, also developed as part of the work, provides a square wave current with no DC component as excitation signal to the electrodes and reads the voltage across them. The developed integrated circuit also includes a temperature sensor, whose produced signal is used to yield the correct humidity measurement. Samples of the integrated circuit were fabricated in 0.35µm CMOS technology and were characterized together with the sensing element. The most relevant characteristics of the developed humidity sensor are: Measuring range: 90%RH max, to avoid condensing; Sensor element sensitivity: 188,83W/%RH at 55%RH; Hysteresis: 3,4% at 55%RH; Operating temperature: 0 to 60oC; Response time: +/-30s. The main contribution of this work is the proposition of a humidity sensor, which is based on a compound of a polymeric sensing element that operates in conjunction with an integrated circuit. The developed integrated circuit performs the necessary conditioning of the involved signals, in addition to include a temperature sensor. The developed humidity sensor has proven to be robust and can be produced at a relative low cost / Mestrado / Eletrônica, Microeletrônica e Optoeletrônica / Mestre em Engenharia Elétrica

University of Macau / Faculty of Science and Technology / Department of Electrical and Electronics Engineering