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published_or_final_version / abstract / Electrical and Electronic Engineering / Master / Master of Philosophy

Areas which require high-temperature MOS circuits are instrumentations for geothermal and petroleum well-logging, space exploration, aero-propulsion systems, and other hostile environments. MOS digital circuits at high temperature are examined as well as the maximum operating temperature of MOS devices. Factors affecting high-temperature operation of these devices, including threshold voltage sensitivity, mobility degradation, leakage current characterization and interactions, zero-TC current in analog applications and reliability considerations, are discussed. Methods to reduce threshold voltage sensitivities, process modifications to reduce leakage current density at high temperature, circuit techniques to eliminate the leakage current effects, diode compensation, CMOS thermal latch-up and MOS scaling rules at high temperature are investigated. Experimental results of epitaxial diodes to verify the leakage current reduction effect are discussed.

This dissertation investigates the implementation of S-parameter based network techniques for the analysis of multiconductor, high speed VLSI integrated circuit and packaging interconnects. The S-parameters can be derived from three categories of input parameters: (1) lossy quasi-static R,L,C and G, (2) lossy frequency dependent (dispersive) R,L,C,G and (3) the propagation constants, Γ, the characteristic impedance, Z(c) and the conductor eigencurrents, I, derived from full wave analysis. The S-parameter network techniques developed allow for: the analysis of periodic waveform excitation, the incorporation of externally measured or calculated scattering parameter data and large system analysis through macro decomposition. The inclusion of non-linear terminations has also been developed.

Reducing circuit complexity to minimize design turnaround time and maximize chip area utilization is the most evident problem in dealing with VLSI layout. Three suggestions have been recommended to reduce circuit complexity. They are using regular modules as design targets, using hierarchical top-down design as a design methodology, and using CAD as a design tool. These three suggestions are the basis of this dissertation project. In this dissertation, three silicon compilers were implemented which take an universal AHPL circuit description as an input and automatically translate it into SLA (Storage Logic Array), PPLA (Path Programmable Logic Array), and ULA (Uncommitted Logic Array) chip layout. The goal is to study different layout algorithms and to derive better algorithms for alternative VLSI structures. In order to make a precise chip area comparison of these three silicon compilers, real SLA and ULA circuits have been designed. Four typical AHPL descriptions of different circuits or varying complexity were chosen as comparison examples. The result shows that the SLA layout requires least area for circuit realization generally. The PPLA approach is the worst one for large scale circuit realization, while the ULA lies in between.

by C.Y. Ho. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1989. / Bibliography: leaves [147]-[148]

by Yeung, Lap Kun. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 96-98). / Abstracts in English and Chinese. / Abstract --- p.ii / Acknowledgements --- p.iv / Table of Contents --- p.v / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Emergence of LTCC Technology --- p.1 / Chapter 1.2 --- Overview of the Work --- p.2 / Chapter 1.3 --- Original Contributions --- p.3 / Chapter 1.4 --- Thesis Organization --- p.4 / Chapter 2 --- Fundamentals of Partial Element Equivalent Circuit Modeling --- p.5 / Chapter 2.1 --- Introduction --- p.5 / Chapter 2.2 --- PEEC Formulation --- p.6 / Chapter 2.2.1 --- Mixed potential integral equation --- p.6 / Chapter 2.2.2 --- Current discretization --- p.7 / Chapter 2.2.3 --- Charge discretization --- p.8 / Chapter 2.2.4 --- Galerkin matching --- p.9 / Chapter 2.3 --- Partial Inductance --- p.11 / Chapter 2.4 --- Partial Capacitance --- p.12 / Chapter 2.5 --- Meshing Scheme and Circuit Interpretation --- p.13 / Chapter 2.6 --- Summary --- p.15 / Chapter 3 --- PEEC Modeling of LTCC RF Circuits using Thin-film Approximation --- p.16 / Chapter 3.1 --- Introduction --- p.16 / Chapter 3.2 --- A Simple LTCC Band-pass Filter --- p.17 / Chapter 3.3 --- Discretization Scheme --- p.18 / Chapter 3.4 --- Quasi-static Green's Functions --- p.21 / Chapter 3.4.1 --- Free-space Green's function --- p.21 / Chapter 3.4.2 --- System with a single ground plane --- p.22 / Chapter 3.4.3 --- System with two ground planes --- p.25 / Chapter 3.5 --- Complex-Image Analysis --- p.25 / Chapter 3.6 --- Partial Inductance --- p.31 / Chapter 3.6.1 --- Strip-to-strip inductance --- p.31 / Chapter 3.6.2 --- System with one or more ground planes --- p.33 / Chapter 3.7 --- Partial Capacitance --- p.34 / Chapter 3.8 --- Numerical and Experimental Results --- p.37 / Chapter 3.9 --- Summary --- p.40 / Chapter 4 --- PEEC Modeling of LTCC RF Circuits using Thin-film Approximation (Via-hole Modeling) --- p.41 / Chapter 4.1 --- Introduction --- p.41 / Chapter 4.2 --- Via-hole Modeling --- p.42 / Chapter 4.2.1 --- Discretization scheme --- p.42 / Chapter 4.2.2 --- Inductance formulae --- p.43 / Chapter 4.2.3 --- Empirical formula --- p.46 / Chapter 4.2.4 --- Edge-effect compensation --- p.48 / Chapter 4.3 --- Numerical and Experimental Results --- p.49 / Chapter 4.4 --- Summary --- p.51 / Chapter 5 --- An Efficient PEEC Algorithm for Modeling of LTCC RF Circuits with Finite Metal Strip Thickness --- p.53 / Chapter 5.1 --- Introduction --- p.53 / Chapter 5.2 --- PEEC Modeling using Thin-film Approximation --- p.54 / Chapter 5.3 --- PEEC Modeling with Finite Metal Thickness --- p.55 / Chapter 5.4 --- Edge-effect Compensation in Inductance Calculation --- p.57 / Chapter 5.5 --- Numerical and Experimental Results --- p.61 / Chapter 5.6 --- Summary --- p.65 / Chapter 6 --- A Compact Second-order LTCC Band-pass Filter with Two Finite Transmission Zeros --- p.66 / Chapter 6.1 --- Introduction --- p.66 / Chapter 6.2 --- Features of the Filter --- p.67 / Chapter 6.3 --- Design Theory --- p.68 / Chapter 6.4 --- LTCC Filter Implementation --- p.70 / Chapter 6.4.1 --- Circuit model --- p.70 / Chapter 6.4.2 --- Physical layout --- p.73 / Chapter 6.5 --- Experimental Results --- p.75 / Chapter 6.6 --- Summary --- p.77 / Chapter 7 --- Concluding Remarks --- p.79 / Chapter 7.1 --- PEEC Modeling --- p.79 / Chapter 7.2 --- Limitations of the Algorithm --- p.80 / Chapter 7.3 --- Further Improvements --- p.81 / Appendix --- p.82 / References --- p.96 / Author's Publications --- p.98

Photocopy of typescript. / Digitized by Kansas Correctional Industries

Thesis. 1976. B.S.--Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. / Microfiche copy available in Archives and Engineering. / by Gustav Laub III. / B.S.