Thesis (Ph. D.)--University of Wisconsin--Madison, 1983. / Typescript. Vita. eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references (leaves 126-132).

Thesis (Ph. D.)--University of Wisconsin--Madison, 1972. / Typescript. Vita. eContent provider-neutral record in process. Description based on print version record. Bibliography: leaves 161-168.

Thesis (M.S.)--Oregon Graduate Center, 1986.

Thesis (M.S.)--Oregon Graduate Center, 1985.

Some portions of real-time computer process control software can be programmed with special purpose high-level languages. A translator writing system for minicomputers is developed to aid in writing translators for those languages. The translator writing system uses an LR(1) grammar analyzer with an LR(1) skeleton parser. XPL is used as the source language for the semantics. An XPL to intermediate language translator has been written to aid in the translation of XPL programs to minicomputer assembly language. A simple macro generator must be written to translate intermediate language programs into various minicomputer assembly languages. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

A brief survey of list-processing languages and list-processors is made, pointing out the shortcomings of each. The need for a practical, applications-oriented list-processor, along with a list of features that would be required, is then presented. A list-processor that is designed to fulfil these requirements is proposed. The presentation includes a detailed description of the storage structure and management algorithms, the primitive routines that have been defined, plus the routines and features available for dynamic storage allocation and list-processing. Finally, a comparison between the proposed list-processor and two available list-processors, SLIP and DYSTAL, is carried out. / Science, Faculty of / Computer Science, Department of / Graduate

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Sorting is one of the more computationally intensive tasks a computer performs. One of the most effective ways to speed up the task of sorting is by using parallel algorithms. When implementing a parallel algorithm, the designer has to make several decisions. Among the decisions are the algorithm and the physical implementation of the algorithm. A dedicated hardware solution is often physically quicker than a software solution. In this thesis, we will investigate the optimization of a hardware implementation of max-min sort. I propose an optimization to the data structures used in the algorithm. The new data structure allows quicker sorting by changing the basic workings of the max-min sort. The results are presented by comparing the new data structure with the original data structure. The thesis also discusses the design and performance issues related to implementing the algorithm in hardware. / Graduation date: 1998

There are a number of well known techniques for extracting parallelism from a given program. They range from hardware implementations, building restructuring compilers or reorganizing of programs so as to specify all the available parallelism. The success rate of any of the known techniques is rather poor over all types of programs. This has pushed the research community to explore new languages and design different architectures to exploit program parallelism. The principles of dataflow architectures have addressed the problem of exploiting parallelism in systems by executing dataflow graphs. These graphs or programs represent data dependencies among instructions and execution of the graph proceeds in a data-driven manner. That is, an instruction is executed as soon as all its operands are available, without waiting for any program counter to sequence its execution, as is the case in conventional von Neumann architectures. In this thesis, data flow graphs are generated during the intermediate compilation of a functional language called SISAL (Streams and Iterations in a Single Assignment Language). The Intermediate Form (IFl) is a graphical language consisting of multiple acyclic function graphs that represent a given program. Each graph consists of a sequence of nodes and edges. The nodes specify the operation and the edges indicate the dependencies between the nodes. The graphs are further connected to each other by means of implicit dependencies. The Automator package developed in this project, preprocesses these multiple IF1 graphs and translates them into a single connected graph. It converts all implicit dependencies into actual ones. Additionally, complex language constructs like For All, loops and if-then-else are treated in special ways together with their nested levels by the Automator. There is virtually no limit to the number of nested levels that can be translated by this package. The Automator's prime contribution is in translating real programs written in SISAL into a specified format required by an allocation algorithm called the Balanced Layered Allocation Scheme (BLAS). BLAS partitions a connected graph into independent tasks and assigns them to processors in a multicomputer system. The problem of program allocation lies in maximizing parallelism while minimizing interprocessor communication costs. Hence, allocation is based on the best choice of communication to execution ratio for each task. BLAS utilizes heuristic rules to find a balance between computation and communication costs in the target system. Here the target architecture is a simulated nCUBE 3E computer, having a hypercube topology. Simulations show that, BLAS is effective in reducing the overall execution time of a program by considering the communication costs on the execution times. The results will help in understanding the effects in packing nodes (grain-packing), routing issues in the network and in general, the allocation problem to any processor in a network. In addition, tasks have also been assigned to adjacent processors only, instead of any processor on the hypercube network. The adjacent allocation to processors helps to determine trade-offs required between achieved speed-ups and the time it takes to completely allocate large graphs on compilation. / Graduation date: 1994

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