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Experiments in solid state electronics using high temperature gas atmospheresGraham, Harl Goronway, 1929- January 1967 (has links)
No description available.
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Probe Modules for Wafer-Level Testing of Gigascale Chips with Electrical and Optical I/O InterconnectsThacker, Hiren Dilipkumar 10 July 2006 (has links)
The use of optical input/output (I/O) interconnects, in addition to electrical I/Os, is a promising approach for achieving high-bandwidth, chip-to-board communications required for future high-performance gigascale chip-based systems. While numerous efforts are underway to investigate the integration of optoelectronics and silicon microelectronics, virtually no work has been reported relating to testing of such chips. The objective of this research is to explore methods that enable wafer-level testing of gigascale chips having electrical and optical I/O interconnects. A major challenge in achieving this is to develop probe modules which would allow high-precision, temporary interconnection of a multitude of electrical and optical I/Os, in a chip-size area, to automated test equipment. A probe module would need to do this in a rapid, step-and-repeat manner across all the chips on the wafer. In this work, two candidate probe modules were devised, batch-fabricated on Si using microfabrication techniques, and successfully demonstrated. The first probe module consists of compliant electrical probes (10^3 probes/cm^2) fabricated alongside grating-in-waveguide optical probes. The second module consists of micro-opto-electro-mechanical-systems (MOEMS)-based microsocket probes (10^4 probes/cm^2) to interface a chip with polymer pillar-based electrical and optical I/Os. High-density through-wafer interconnects are an essential attribute in both probe substrates for transferring electrical and optical signals to the substrate back-side. Fabrication and characterization of metal-clad, metal-filled, and polymer-filled through-wafer interconnects as well as process integration with probe substrate fabrication are described and numerous possible redistribution schemes are explicated. Chips with optical and electrical I/Os are an emerging technology, and one that test engineers are likely to encounter in the near future. The contributions of this thesis are to help understand and address the issues relating to joint electrical and optical testing during manufacturing.
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