Stress sensitivity of a 16 - bit D/A converter in a molded plastic DIP has been studied. Device performance was shown to change as a function of package stress. The effects of die position in the package and the presence or absence of die coat on package stress and device performance were determined. Finite element methods were employed for system analysis. Device stress sensitivity was attributed to diffused bit transistors and the mechanism assigned to nonuniformity of stress on the device bit transistors. Die coat (silicone gel) was shown to reduce normal and shear stresses and have little or no effect on X-axial stresses. Lowering the die in the package was shown to increase the X-axial stress uniformity from the die center to edge for die-coated parts and alter the value of shear stresses near the die edge for parts without die coat.

Effective power delivery in Double-sided 3-D glass interposer packages was proposed, investigated, and demonstrated towards achieving high logic-to-memory bandwidth. Such 3-D interposers enable a simpler alternative to direct 3-D stacking by providing low-loss, wide-I/O channels between the logic device on one side of the ultra-thin glass interposer and memory stack on the other side, eliminating the need for complex TSVs in the logic die. A simplified PDN design approach with power-ground planes was proposed to overcome resonance challenges from (a) added parasitic inductance in the lateral power delivery path from the printed wiring board (PWB), due to die placement on the bottom side of the interposer, and (b) the low-loss property of the glass substrate. Based on this approach, this dissertation developed three important suppression solutions using, (a) the 3-D interposer package configuration, (b) the selection of embedded and SMT-based decoupling capacitors, and (c) coaxial power-ground planes with TPVs. The self-impedance of the 3-D glass interposer PDN was simulated using electromagnetic solvers, including printed-wiring-board (PWB) and chip-level models. Two-metal and four-metal layer test vehicles were fabricated on 30-μm and 100-μm thick glass substrates using a panel-based double-side fabrication process, for potential lower cost and improved electrical performance. The PDN test structures were characterized upto 20 GHz, to demonstrate the measured verification of (a) 3-D glass interposer power delivery network and (b) resonance suppression. The data and analysis presented in this dissertation prove that the objectives of this research were met successfully, leading to the first demonstration of effective PDN design in ultra-thin (30-100μm), and 3-D double-sided glass BGA packages, by suppressing the PDN noise from mode resonances.

Sham Chiu Wing. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 107-113). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivations --- p.1 / Chapter 1.2 --- Progress on the Problem --- p.2 / Chapter 1.3 --- Our Contributions --- p.3 / Chapter 1.4 --- Thesis Organization --- p.5 / Chapter 2 --- Preliminaries --- p.6 / Chapter 2.1 --- Introduction --- p.6 / Chapter 2.1.1 --- The Role of Floorplanning --- p.6 / Chapter 2.1.2 --- Wirelength Estimation --- p.7 / Chapter 2.1.3 --- Different Types of Floorplan --- p.8 / Chapter 2.2 --- Representations of Floorplan --- p.10 / Chapter 2.2.1 --- Polish Expressions --- p.10 / Chapter 2.2.2 --- Sequence Pair --- p.11 / Chapter 2.2.3 --- Bounded-Sliceline Grid (BSG) Structure --- p.13 / Chapter 2.2.4 --- O-Tree --- p.14 / Chapter 2.2.5 --- B*-Tree --- p.16 / Chapter 2.2.6 --- Corner Block List --- p.18 / Chapter 2.2.7 --- Twin Binary Tree --- p.19 / Chapter 2.2.8 --- Comparisons between Different Representations --- p.20 / Chapter 2.3 --- Algorithms of Floorplan Design --- p.20 / Chapter 2.3.1 --- Constraint Based Floorplanning --- p.21 / Chapter 2.3.2 --- Integer Programming Based Floorplanning --- p.21 / Chapter 2.3.3 --- Neural Learning Based Floorplanning --- p.22 / Chapter 2.3.4 --- Rectangular Dualization --- p.22 / Chapter 2.3.5 --- Simulated Annealing --- p.23 / Chapter 2.3.6 --- Genetic Algorithm --- p.23 / Chapter 2.4 --- Summary --- p.24 / Chapter 3 --- Literature Review on Interconnect-Driven Floorplanning --- p.25 / Chapter 3.1 --- Introduction --- p.25 / Chapter 3.2 --- Simulated Annealing Approach --- p.25 / Chapter 3.2.1 --- """Pepper - A Timing Driven Early Floorplanner""" --- p.25 / Chapter 3.2.2 --- """A Timing Driven Block Placer Based on Sequence Pair Model""" --- p.26 / Chapter 3.2.3 --- """Integrated Floorplanning and Interconnect Planning""" --- p.27 / Chapter 3.2.4 --- """Interconnect Driven Floorplanning with Fast Global Wiring Planning and Optimization""" --- p.27 / Chapter 3.3 --- Genetic Algorithm Approach --- p.28 / Chapter 3.3.1 --- "“Timing Influenced General-cell Genetic Floorplanning""" --- p.28 / Chapter 3.4 --- Force Directed Approach --- p.29 / Chapter 3.4.1 --- """Timing Influenced Force Directed Floorplanning""" --- p.29 / Chapter 3.5 --- Congestion Planning --- p.30 / Chapter 3.5.1 --- """On the Behavior of Congestion Minimization During Placement""" --- p.30 / Chapter 3.5.2 --- """Congestion Minimization During Placement""" --- p.31 / Chapter 3.5.3 --- "“Estimating Routing Congestion Using Probabilistic Anal- ysis""" --- p.31 / Chapter 3.6 --- Buffer Planning --- p.32 / Chapter 3.6.1 --- """Buffer Block Planning for Interconnect Driven Floor- planning""" --- p.32 / Chapter 3.6.2 --- """Routability Driven Repeater Block Planning for Interconnect- centric Floorplanning""" --- p.33 / Chapter 3.6.3 --- """Provably Good Global Buffering Using an Available Block Plan""" --- p.34 / Chapter 3.6.4 --- "“Planning Buffer Locations by Network Flows""" --- p.34 / Chapter 3.6.5 --- """A Practical Methodology for Early Buffer and Wire Re- source Allocation""" --- p.35 / Chapter 3.7 --- Summary --- p.36 / Chapter 4 --- Floorplanner with Fixed Buffer Planning [34] --- p.37 / Chapter 4.1 --- Introduction --- p.37 / Chapter 4.2 --- Overview of the Floorplanner --- p.38 / Chapter 4.3 --- Congestion Model --- p.38 / Chapter 4.3.1 --- Construction of Grid Structure --- p.39 / Chapter 4.3.2 --- Counting the Number of Routes at a Grid --- p.40 / Chapter 4.3.3 --- Buffer Location Computation --- p.41 / Chapter 4.3.4 --- Counting Routes with Blocked Grids --- p.42 / Chapter 4.3.5 --- Computing the Probability of Net Crossing --- p.43 / Chapter 4.4 --- Time Complexity --- p.44 / Chapter 4.5 --- Simulated Annealing --- p.45 / Chapter 4.6 --- Wirelength Estimation --- p.46 / Chapter 4.6.1 --- Center-to-center Estimation --- p.47 / Chapter 4.6.2 --- Corner-to-corner Estimation --- p.47 / Chapter 4.6.3 --- Intersection-to-intersection Estimation --- p.48 / Chapter 4.7 --- Multi-pin Nets Handling --- p.49 / Chapter 4.8 --- Experimental Results --- p.50 / Chapter 4.9 --- Summary --- p.51 / Chapter 5 --- Floorplanner with Flexible Buffer Planning [35] --- p.53 / Chapter 5.1 --- Introduction --- p.53 / Chapter 5.2 --- Overview of the Floorplanner --- p.54 / Chapter 5.3 --- Congestion Model --- p.55 / Chapter 5.3.1 --- Probabilistic Model with Variable Interval Buffer Inser- tion Constraint --- p.57 / Chapter 5.3.2 --- Time Complexity --- p.61 / Chapter 5.4 --- Buffer Planning --- p.62 / Chapter 5.4.1 --- Estimation of Buffer Usage --- p.62 / Chapter 5.4.2 --- Estimation of Buffer Resources --- p.69 / Chapter 5.5 --- Two-phases Simulated Annealing --- p.70 / Chapter 5.6 --- Wirelength Estimation --- p.72 / Chapter 5.7 --- Multi-pin Nets Handling --- p.73 / Chapter 5.8 --- Experimental Results --- p.73 / Chapter 5.9 --- Remarks --- p.76 / Chapter 5.10 --- Summary --- p.76 / Chapter 6 --- Global Router --- p.77 / Chapter 6.1 --- Introduction --- p.77 / Chapter 6.2 --- Overview of the Global Router --- p.77 / Chapter 6.3 --- Buffer Insertion Constraint and Congestion Constraint --- p.78 / Chapter 6.4 --- Multi-pin Nets Handling --- p.79 / Chapter 6.5 --- Routing Methodology --- p.79 / Chapter 6.6 --- Implementation --- p.80 / Chapter 6.7 --- Summary --- p.86 / Chapter 7 --- Interconnect-Driven Floorplanning by Alternative Packings --- p.87 / Chapter 7.1 --- Introduction --- p.87 / Chapter 7.2 --- Overview of the Method --- p.87 / Chapter 7.3 --- Searching Alternative Packings --- p.89 / Chapter 7.3.1 --- Rectangular Supermodules in Sequence Pair --- p.89 / Chapter 7.3.2 --- Finding rearrangable module sets --- p.90 / Chapter 7.3.3 --- Alternative Sequence Pairs --- p.94 / Chapter 7.4 --- Implementation --- p.97 / Chapter 7.4.1 --- Re-calculation of Interconnect Cost --- p.98 / Chapter 7.4.2 --- Cost Function --- p.101 / Chapter 7.4.3 --- Time Complexity --- p.101 / Chapter 7.5 --- Experimental Results --- p.101 / Chapter 7.6 --- Summary --- p.103 / Chapter 8 --- Conclusion --- p.105 / Bibliography --- p.107

Wong Wai-Chiu. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 94-101). / Abstracts in English and Chinese. / Abstract --- p.iii / Abstract in Chinese --- p.v / Acknowledgements --- p.vi / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivations --- p.2 / Chapter 1.2 --- Progress on Interconnect-driven Floorplanning --- p.4 / Chapter 1.2.1 --- Congestion Optimization --- p.4 / Chapter 1.2.2 --- Buffer Insertion --- p.5 / Chapter 1.3 --- Contributions --- p.6 / Chapter 1.4 --- Organization of this Thesis --- p.7 / Chapter 2 --- "VLSI Circuit Design, Physical Design Cycle and Floorplanning" --- p.8 / Chapter 2.1 --- VLSI Circuit Design Cycle --- p.9 / Chapter 2.2 --- Physical Design Cycle --- p.10 / Chapter 2.2.1 --- Circuit Partitioning --- p.10 / Chapter 2.2.2 --- Floorplanning and Placement --- p.11 / Chapter 2.2.3 --- Routing --- p.12 / Chapter 2.2.4 --- Compaction --- p.12 / Chapter 2.3 --- Introduction to Floorplanning --- p.13 / Chapter 2.4 --- Types of Floorplan --- p.14 / Chapter 2.5 --- Simulated Annealing --- p.15 / Chapter 2.6 --- Floorplan Representation --- p.16 / Chapter 2.6.1 --- Polish Expression --- p.17 / Chapter 2.6.2 --- Sequence Pair --- p.18 / Chapter 2.6.3 --- Twin Binary Tree --- p.20 / Chapter 2.6.4 --- Comparisons between Different Floorplan Representations --- p.21 / Chapter 2.7 --- Chapter Summary --- p.22 / Chapter 3 --- Interconnect Optimization in Floorplanning --- p.24 / Chapter 3.1 --- Routing Congestion Optimization --- p.25 / Chapter 3.2 --- Buffer Planning --- p.26 / Chapter 3.3 --- Wire Sizing --- p.28 / Chapter 3.4 --- Simultaneous Wire Sizing and Buffer Planning --- p.30 / Chapter 3.5 --- Literature Review on Interconnect-driven Floorplanning --- p.31 / Chapter 3.5.1 --- Congestion Optimization --- p.31 / Chapter 3.5.2 --- Buffer Insertion --- p.36 / Chapter 3.6 --- Chapter Summary --- p.40 / Chapter 4 --- Floorplanning with Congestion Optimization and Buffer Block Planning --- p.41 / Chapter 4.1 --- Floorplanner Overview --- p.42 / Chapter 4.1.1 --- Grid Structure and Blocked Grids --- p.44 / Chapter 4.1.2 --- Buffer Block Planning --- p.44 / Chapter 4.2 --- Elmore Delay Model --- p.46 / Chapter 4.2.1 --- Wire Sizing --- p.47 / Chapter 4.2.2 --- Buffer Insertion --- p.48 / Chapter 4.2.3 --- Simultaneous Buffer Insertion and Wire Sizing --- p.49 / Chapter 4.3 --- Dynamic Programming Approach for Buffer Planning and Wire Sizing --- p.49 / Chapter 4.4 --- Implementation of the Dynamic Programming Approach --- p.51 / Chapter 4.5 --- Lookup Table Construction --- p.53 / Chapter 4.6 --- Congestion Model --- p.55 / Chapter 4.7 --- Cost Function --- p.56 / Chapter 4.8 --- Algorithm --- p.56 / Chapter 4.9 --- Experimental Results --- p.57 / Chapter 4.9.1 --- Experimental Results on Simultaneous Buffer Insertion and Wire Sizing --- p.57 / Chapter 4.9.2 --- Experimental Results of using the Table Lookup Approach --- p.58 / Chapter 4.10 --- Chapter Summary --- p.60 / Chapter 5 --- Floorplanning with Flexible Buffer Planning and Routability Op- timization --- p.63 / Chapter 5.1 --- Floorplanner Overview --- p.64 / Chapter 5.1.1 --- Constraints in Buffer Locations --- p.64 / Chapter 5.2 --- Congestion Estimation --- p.66 / Chapter 5.3 --- Buffer Location Computation --- p.67 / Chapter 5.3.1 --- Feasible Locations for Buffer Insertion --- p.67 / Chapter 5.3.2 --- Cost of Grids for Buffer Insertion --- p.69 / Chapter 5.3.3 --- Dynamic Programming Approach for Selecting Buffer Lo- cation of a Net --- p.70 / Chapter 5.3.4 --- An Example --- p.70 / Chapter 5.4 --- Congestion Model --- p.72 / Chapter 5.4.1 --- Net-count Congestion Model --- p.72 / Chapter 5.4.2 --- Grid-count Congestion Model --- p.74 / Chapter 5.5 --- Buffer Location Bounds --- p.75 / Chapter 5.6 --- Net Grouping --- p.77 / Chapter 5.7 --- Cost Function --- p.79 / Chapter 5.8 --- Algorithm . --- p.79 / Chapter 5.9 --- Experimental Results --- p.79 / Chapter 5.9.1 --- Net Grouping Factor --- p.80 / Chapter 5.9.2 --- Experimental Results of our Floorplanner --- p.80 / Chapter 5.9.3 --- Comparison on Different Congestion Models --- p.82 / Chapter 5.10 --- Chapter Summary --- p.83 / Chapter 6 --- Conclusion --- p.86 / Chapter 6.1 --- Discussion --- p.87 / Chapter 6.2 --- Improvements --- p.88 / Chapter 6.2.1 --- Net Grouping and Ordering --- p.88 / Chapter 6.2.2 --- Congestion Modelling --- p.89 / Appendix --- p.90 / Chapter A --- Overview on VLSI Technology --- p.91 / Chapter A.l --- Moore's Law and Trends in VLSI --- p.91 / Chapter A.2 --- Scaling --- p.93 / Bibliography --- p.101

by Ng Chi-Keung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1998. / Includes bibliographical references (leaves 127-134). / Abstract also in Chinese. / Abstract --- p.2 / 摘要 --- p.3 / Acknowledgements --- p.4 / Chapter Chapter 1 --- Introduction --- p.7 / Chapter Chapter 2 --- Packaging Effects of Integrated Circuits --- p.9 / Chapter 2.1 --- The Structure of the IC Package --- p.9 / Chapter 2.2 --- Microstrip Discontinuities --- p.11 / Chapter Chapter 3 --- The Finite-Difference Time-Domain Method --- p.19 / Chapter 3.1 --- Basic Theory --- p.19 / Chapter 3.2 --- Stability Criterion --- p.25 / Chapter 3.3 --- Formulation of Source --- p.30 / Chapter A. --- Source Function --- p.30 / Chapter (i) --- Sinusoidal --- p.30 / Chapter (ii) --- Gaussian Pulse --- p.31 / Chapter B. --- Source Realization --- p.36 / Chapter (i) --- Electric Field Source --- p.36 / Chapter (ii) --- Lumped Source --- p.38 / Chapter (iii) --- Current Source --- p.40 / Chapter C. --- Source Placement --- p.41 / Chapter 3.4 --- Parameter Extraction --- p.42 / Chapter A. --- Voltage and Current --- p.42 / Chapter B. --- Characteristic Impedance --- p.44 / Chapter C. --- Effective Dielectric Constant --- p.45 / Chapter D. --- Scattering Parameters --- p.46 / Chapter 3.5 --- Termination and Boundary Treatment --- p.48 / Chapter A. --- Perfect Electric Conductor (PEC) --- p.48 / Chapter B. --- Perfect Magnetic Conductor (PMC) --- p.49 / Chapter C. --- Interface between Two Materials --- p.50 / Chapter 3.6 --- Perfectly Matched Layer (PML) --- p.54 / Chapter A. --- Theory of PML in Three Dimensions --- p.56 / Chapter B. --- Incorporation of PML as Absorbing Boundary Condition (ABC) --- p.65 / Chapter C. --- Discretization of Maxwell's Equations in PML --- p.73 / Chapter 3.7 --- Flowcharts --- p.75 / Chapter A. --- Free Space Radiation by a Dipole Antenna --- p.77 / Chapter B. --- Parameters of a Microstrip Line --- p.79 / Chapter C. --- Scattering Parameters of Planar Network --- p.85 / Chapter 3.8 --- Summary --- p.87 / Chapter Chapter 4 --- Effects of Ground Via Allocation --- p.88 / Chapter 4.1 --- Introduction --- p.88 / Chapter 4.2 --- Simulation and Experimental Results --- p.91 / Chapter 4.3 --- Equivalent Circuit Modelling --- p.108 / Chapter 4.4 --- Summary --- p.124 / Chapter Chapter 5 --- Conclusions --- p.125 / Chapter Chapter 6 --- Recommendation for Future Work --- p.126 / References --- p.127 / Publication --- p.134

Leung, Chi Kwan. / Thesis submitted in: December 2007. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references (leaves 66-68). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Literature Review on Fixed-outline Floorplanning --- p.5 / Chapter 2.1 --- General Floorplanning --- p.5 / Chapter 2.1.1 --- Simulated Annealing --- p.6 / Example - Normalized Polish Expression --- p.9 / Example - Sequence Pair Representation --- p.15 / Example - Corner Block List --- p.19 / Chapter 2.1.2 --- Genetic Algorithm --- p.24 / Chapter 2.1.3 --- Mixed Integer Linear Programming --- p.25 / Chapter 2.1.4 --- Geometric Programming --- p.25 / Chapter 2.1.5 --- Discussion --- p.26 / Advantages of using Simulated Annealing --- p.26 / Disadvantages of using Simulated Annealing --- p.27 / Chapter 2.2 --- Fixed-outline Floorplanning --- p.28 / Chapter 2.2.1 --- Motivation --- p.28 / Chapter 2.2.2 --- Dimension Based Cost Function --- p.30 / Chapter 2.2.3 --- Aspect Ratio Based Cost Function --- p.32 / Chapter 2.2.4 --- Evolutionary Search --- p.33 / Chapter 2.2.5 --- Instance Augmentation --- p.35 / Chapter 3 --- Predictive Rating with Fixed Outline Constraints --- p.39 / Chapter 3.1 --- Introduction --- p.39 / Chapter 3.2 --- Motivation --- p.40 / Chapter 3.3 --- Predictive Rating Scheme --- p.44 / Chapter 3.3.1 --- Area --- p.45 / Chapter 3.3.2 --- Dimensions --- p.46 / Chapter 3.3.3 --- Aspect Ratio --- p.47 / Chapter 3.3.4 --- Overall Equation for Predictive Rating --- p.48 / Chapter 3.4 --- Integration into the Floorplanner --- p.49 / Chapter 3.5 --- Experimental Results --- p.50 / Chapter 3.5.1 --- Accuracy of Predictive Rating --- p.50 / Chapter 3.5.2 --- Test One --- p.52 / Chapter 3.5.3 --- Test Two --- p.57 / Chapter 3.6 --- Conclusion --- p.61 / Chapter 4 --- Conclusion --- p.64 / Bibliography --- p.66

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Materials Science and Engineering Program, 2006. / Includes bibliographical references.

All power electronics consist of solid state devices that generate heat. Managing the temperature of these devices is critical to their performance and reliability. Traditional methods involving liquid-cooling systems are expensive and require additional equipment for operation. Air-cooling systems are less expensive but are typically less effective at cooling the electronic devices. The cooling system that is used depends on the specific application. Until recently, silicon based devices have been used for the solid-state devices in power electronics. Newly developed silicon-carbide based wide band gap devices operate at maximum temperatures higher than traditional silicon devices. Due to the permissible increase in operating temperatures, it has been proposed to develop an air-cooling system for an inverter consisting of silicon carbide devices. This thesis presents recent research efforts to develop the proposed air-cooling system. The thermal performance of the each design iteration was determined by numerical simulations via the finite element method in both steady state and transient mode using COMSOL Multi-physics software version 3.5a. For all simulations presented in this thesis, the heat dissipated in the MOSFETS and diodes are specified as functions of current, voltage, switching frequency, and junction temperature. For both the steady state and transient simulations, the junction temperature was determined iteratively. Additionally in the transient simulations, the current distribution is a function of time and was deduced from the EPA US06 drive cycle. After several design iterations, a thermally feasible design has been reached. This design is presented in detail in this thesis. Under transient simulations of the final design, the maximum junction temperatures were determined to be below 146 ºC for air flow rates of 30 and 60 CFM, which is substantially lower than the 250 ºC maximum allowable junction temperature of Si-C devices. However for steady state simulations, junction temperatures were found to be much higher than the transient simulations. It was determined that a minimum flow rate of 50 CFM is required to meet the temperature requirements of the Si-C devices under steady state operating conditions. The power density of this air-cooled final design is 11.75 kW/L, and it is competitive with liquid-cooled systems.

The generalized theory of thermoelasticity was employed to characterize the coupled thermal and mechanical wave propagation in high performance microelectronic packages. Application of a Gaussian heat source of spectral profile similar to high performance devices was shown to induce rapid thermal and mechanical transient phenomena. The stresses and temporal gradient of stresses (power density) induced by the thermal and mechanical disturbances were analyzed using the Gabor Wavelet Transform (GWT). The arrival time of frequency components and their magnitude was studied at various locations in the package. Comparison of the results from the classical thermoelasticity theory and generalized theory was also conducted. It was found that the two theories predict vastly different results in the vicinity of the heat source but that the differences diminish within a larger time window. Results from both theories indicate that the rapid thermal-mechanical waves cause high frequency, broadband stress waves to propagate through the package for a very short period of time. The power density associated with these stress waves was found to be of significant magnitude indicating that even though the effect, titled short time scale effect, is short lived, it could have significant impact on package reliability. The high frequency and high power density associated with the stress waves indicate that the probability of sub-micron cracking and/or delamination due to short time scale effect is high. The findings demonstrate that in processes involving rapid thermal transients, there is a non-negligible transient phenomenon worthy of further investigation.

It is the objective of this work to focus on heat dissipation in gallium nitride based solid-state logic devices as well as optoelectronic devices, a major technical challenge. With a direct band gap that is tunable through alloying between 0.7-3.8 eV, this material provides an enabling technology for power generation, telecommunications, power electronics, and advanced lighting sources. Previously, advances in these areas were limited by the availability of high quality material and growth methods, resulting in high dislocation densities and impurities. Within the last 40 years improvements in epitaxial growth methods such as lateral epitaxial overgrowth (LEO), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), and metal organic chemical vapor deposition (MOCVD), has enabled electron mobilities greater than 1600 cm2V/s, with dislocation densities less than 109/cm2. Increases in device performance with improved materials have now been associated with an increase in power dissipation (>1kW/cm2) that is limiting further development. In the following work thermophysical material of III-V semiconducting thin films and associated substrates are presented. Numerical modeling coupled with optical (micro-IR imaging and micro-Raman Spectroscopy) methods was utilized in order to study the heat carrier motion and the temperature distribution in an operating device. Results from temperature mapping experiments led to an analysis for design of next generation advancements in electronics packaging.