It is the objective of this work to focus on heat dissipation in gallium nitride based solid-state logic devices as well as optoelectronic devices, a major technical challenge. With a direct band gap that is tunable through alloying between 0.7-3.8 eV, this material provides an enabling technology for power generation, telecommunications, power electronics, and advanced lighting sources. Previously, advances in these areas were limited by the availability of high quality material and growth methods, resulting in high dislocation densities and impurities. Within the last 40 years improvements in epitaxial growth methods such as lateral epitaxial overgrowth (LEO), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), and metal organic chemical vapor deposition (MOCVD), has enabled electron mobilities greater than 1600 cm2V/s, with dislocation densities less than 109/cm2. Increases in device performance with improved materials have now been associated with an increase in power dissipation (>1kW/cm2) that is limiting further development. In the following work thermophysical material of III-V semiconducting thin films and associated substrates are presented. Numerical modeling coupled with optical (micro-IR imaging and micro-Raman Spectroscopy) methods was utilized in order to study the heat carrier motion and the temperature distribution in an operating device. Results from temperature mapping experiments led to an analysis for design of next generation advancements in electronics packaging.

The generalized theory of thermoelasticity was employed to characterize the coupled thermal and mechanical wave propagation in high performance microelectronic packages. Application of a Gaussian heat source of spectral profile similar to high performance devices was shown to induce rapid thermal and mechanical transient phenomena. The stresses and temporal gradient of stresses (power density) induced by the thermal and mechanical disturbances were analyzed using the Gabor Wavelet Transform (GWT). The arrival time of frequency components and their magnitude was studied at various locations in the package. Comparison of the results from the classical thermoelasticity theory and generalized theory was also conducted. It was found that the two theories predict vastly different results in the vicinity of the heat source but that the differences diminish within a larger time window. Results from both theories indicate that the rapid thermal-mechanical waves cause high frequency, broadband stress waves to propagate through the package for a very short period of time. The power density associated with these stress waves was found to be of significant magnitude indicating that even though the effect, titled short time scale effect, is short lived, it could have significant impact on package reliability. The high frequency and high power density associated with the stress waves indicate that the probability of sub-micron cracking and/or delamination due to short time scale effect is high. The findings demonstrate that in processes involving rapid thermal transients, there is a non-negligible transient phenomenon worthy of further investigation.

The trend to high I/O density, performance and miniaturization at low cost is driving the industry towards shrinking interposer design rules, requiring a new set of packaging technologies. Low-CTE packages from silicon, glass and low-CTE organic substrates enable high interconnection density, high reliability and integration of system components. However, the large CTE mismatch between the package and the board presents reliability challenges for the board-level interconnections. Novel stress-relief structures that can meet reliability requirements along with electrical performance while meeting the cost constraints are needed to address these challenges. This thesis focuses on a comprehensive methodology starting with modeling, design, fabrication and characterization to validate such stress-relief structures. This study specifically explores SMT-compatible stress-relief microwire arrays in thin polymer carriers as a unique and low-cost solution for reliable board-level interconnections between large low-CTE packages and printed wiring boards. The microwire arrays are pre-fabricated in ultra-thin carriers using low-cost manufacturing processes such as laser vias and copper electroplating, which are then assembled in between the interposer and printed wiring board (PWB) as stress-relief interlayers. The microwire array results in dramatic reduction in solder stresses and strains, even with larger interposer sizes (20 mm × 20 mm), at finer pitch (400 microns), without the need for underfill. The parallel wire arrays result in low resistance and inductance, and therefore do not degrade the electrical performance. The scalability of the structures and the unique processes, from micro to nanowires, provides extendibility to finer pitch and larger package sizes. Finite element method (FEM) was used to study the reliability of the interconnections to provide guidelines for the test vehicle design. The models were built in 2.5D geometries to study the reliability of 400 µm-pitch interconnections with a 100 µm thick, 20 mm × 20 mm silicon package that was SMT-assembled onto an organic printed wiring board. The performance of the microwire array interconnection is compared to that of ball grid array (BGA) interconnections, in warpage, equivalent plastic strain and projected fatigue life. A unique set of materials and processes was used to demonstrate the low-cost fabrication of microwire arrays. Copper microwires with 12 µm diameter and 50 µm height were fabricated on both sides of a 50 µm thick, thermoplastic polymer carrier using dryfilm based photolithography and bottom-up electrolytic plating. The copper microwire interconnections were assembled between silicon interposer and FR-4 PWB through SMT-compatible process. Thermal mechanical reliability of the interconnections was characterized by thermal cycling test from -40°C to 125°C. The initial fatigue failure in the interconnections was identified at 700 cycles in the solder on the silicon package side, which is consistent with the modeling results. This study therefore demonstrated a highly-reliable and SMT-compatible solution for board-level interconnections between large low-CTE packages and printed wiring board.

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Emerging I/O density and bandwidth requirements are driving packages to low-CTE silicon, glass and organic substrates for higher wiring density and reliability of interconnections and Cu-low k dielectrics. These are needed for high performance applications as 2.5D packages in large-size, and also as ultra-thin packages for consumer applications that are directly assembled on the board without the need for an intermediate package. The trend to low-CTE packages (CTE of 3-8ppm/°C), however, creates large CTE mismatch with the board on which they are assembled. Interconnection reliability is, therefore, a major concern when low CTE interposers are surface mounted onto organic system boards via solder joints. This reliability concern is further aggravated with large package sizes and finer pitch. For wide acceptance of low CTE packages in high volume production, it is also critical to assemble them on board using standard Surface Mount Technologies (SMT) without the need for under-fill. This research aims to demonstrate reliable 400 micron pitch solder interconnections from low CTE glass interposers directly assembled onto organic boards by overcoming the above challenges using two approaches; 1) Stress-relief dielectric build up layers on the back of the interposer, 2) Polymer collar around the solder bumps for shear stress re-distribution. A comprehensive methodology based on modeling, design, test vehicle fabrication and characterization is employed to study and demonstrate the efficacy of these approaches in meeting the interposer-to-board interconnection requirements. The effect of varying geometrical and material properties of both build-up layers and polymer collar is studied through Finite Element Modeling. Interposers were designed and fabricated with the proposed approaches to demonstrate process feasibility.

Advancements in the semiconductor industry have lead to the miniaturization of components and increased power densities, resulting in thermal management issues. In response to this shift, finding multifunctional materials with excellent thermal conductivity and tailored electrical properties are becoming increasingly important. For this research thesis, three different studies were conducted to develop and characterize thermally conductive polymer composites. In the first study, a PPS matrix was combined with different types of carbon-based fillers to determine the effects of filler’s size, shape, and orientation on thermal conductivity. In the second study, effects of adding ceramic- and carbon- based fillers on the tailored thermal and electrical properties of composites were investigated. Lastly, the possibility of improving the thermal conductivity by introducing and aligning polymer fibers in the composites was investigated. The composites were characterized with respect to their physical, thermal, and electrical properties to propose possibilities of application in the electronic packaging industries.