This research characterizes the thermal stress resulting from temperature gradients in hybrid solid oxide fuel cells that are processed using a novel oxide powder slurry technology developed at Georgia Tech. The hybrid solid oxide fuel cell is composed of metallic interconnect and ceramic electrolyte constituents with integral mechanical bonds formed during high temperature processing steps. A combined thermo-mechanical analysis approach must be implemented to evaluate a range of designs for power output and structural integrity. As an alternative to costly CFD analysis, approximate finite difference techniques that are more useful in preliminary design are developed to analyze the temperature distributions resulting from a range of fuel cell geometries and materials. The corresponding thermal stresses are then calculated from the temperature fields using ABAQUS. This model analyzes the manufacturing, start-up, and steady state operating conditions of the hybrid solid oxide fuel cell.

Two subjects are included in this thesis; one is to construct the Coffin-Manson equation of the unleaded SnAgCu solder according to the experimental results provided by the Metal Research Laboratory (MRL) of Industrial Technologies Research Institute (ITRI). The results of CSP thermal cycle fatigue and SOJ pull tests and the corresponding stress and strain distributions solved from FEM analyses have been used to derive the Coffin-Manson equation for the SnAgCu solder. The other subject is to investigate the effect of CTE mismatch on the fatigue life of solder balls in the opto-electronic packaging. The solidified shapes of the different solder balls after undergoing the re-flow process are predicted by employing the Surface Evolver package program. The FEA meshes of the solidified solder balls in opto-electronic packaging are built according to the output results of the Surface Evolver program. The maximum equivalent plastic shear strain range of the solder after under one thermal cycle process is calculated by employing the MARC finite element package. The fatigue lives of solder balls under different arrangements are estimated according to the proposed Coffin-Manson equation. The effect of solder ball parameters, i.e. solder volume, solder offset distance, solder DNP and solder material on the reliability of different solder balls has also been explored in this thesis.

The trend to high I/O density, performance and miniaturization at low cost is driving the industry towards shrinking interposer design rules, requiring a new set of packaging technologies. Low-CTE packages from silicon, glass and low-CTE organic substrates enable high interconnection density, high reliability and integration of system components. However, the large CTE mismatch between the package and the board presents reliability challenges for the board-level interconnections. Novel stress-relief structures that can meet reliability requirements along with electrical performance while meeting the cost constraints are needed to address these challenges. This thesis focuses on a comprehensive methodology starting with modeling, design, fabrication and characterization to validate such stress-relief structures. This study specifically explores SMT-compatible stress-relief microwire arrays in thin polymer carriers as a unique and low-cost solution for reliable board-level interconnections between large low-CTE packages and printed wiring boards. The microwire arrays are pre-fabricated in ultra-thin carriers using low-cost manufacturing processes such as laser vias and copper electroplating, which are then assembled in between the interposer and printed wiring board (PWB) as stress-relief interlayers. The microwire array results in dramatic reduction in solder stresses and strains, even with larger interposer sizes (20 mm × 20 mm), at finer pitch (400 microns), without the need for underfill. The parallel wire arrays result in low resistance and inductance, and therefore do not degrade the electrical performance. The scalability of the structures and the unique processes, from micro to nanowires, provides extendibility to finer pitch and larger package sizes. Finite element method (FEM) was used to study the reliability of the interconnections to provide guidelines for the test vehicle design. The models were built in 2.5D geometries to study the reliability of 400 µm-pitch interconnections with a 100 µm thick, 20 mm × 20 mm silicon package that was SMT-assembled onto an organic printed wiring board. The performance of the microwire array interconnection is compared to that of ball grid array (BGA) interconnections, in warpage, equivalent plastic strain and projected fatigue life. A unique set of materials and processes was used to demonstrate the low-cost fabrication of microwire arrays. Copper microwires with 12 µm diameter and 50 µm height were fabricated on both sides of a 50 µm thick, thermoplastic polymer carrier using dryfilm based photolithography and bottom-up electrolytic plating. The copper microwire interconnections were assembled between silicon interposer and FR-4 PWB through SMT-compatible process. Thermal mechanical reliability of the interconnections was characterized by thermal cycling test from -40°C to 125°C. The initial fatigue failure in the interconnections was identified at 700 cycles in the solder on the silicon package side, which is consistent with the modeling results. This study therefore demonstrated a highly-reliable and SMT-compatible solution for board-level interconnections between large low-CTE packages and printed wiring board.

Using experimentally measured temperature-process-dependent model parameters, the failure analysis and life prediction were conducted for Atmospheric Plasma Sprayed Thermal Barrier Coatings (APS-TBCs) and electron beam physical vapor deposition thermal barrier coatings (EB-PVD TBCs) with Pt-modified -NiAl bond coats deposited on Ni-base single crystal superalloys. For APS-TBC system, a residual stress model for the top coat of APS-TBC was proposed and then applied to life prediction. The capability of the life model was demonstrated using temperature-dependent model parameters. Using existing life data, a comparison of fitting approaches of life model parameters was performed. The role of the residual stresses distributed at each individual coating layer was explored and their interplay on the coating’s delamination was analyzed. For EB-PVD TBCs, based on failure mechanism analysis, two newly analytical stress models from the valley position of top coat and ridge of bond coat were proposed describing stress levels generated as consequence of the coefficient of thermal expansion (CTE) mismatch between each layers. The thermal stress within TGO was evaluated based on composite material theory, where effective parameters were calculated. The lifetime prediction of EB-PVD TBCs was conducted given that the failure analysis and life model were applied to two failure modes A and B identified experimentally for thermal cyclic process. The global wavelength related to interface rumpling and its radius curvature were identified as essential parameters in life evaluation, and the life results for failure mode A were verified by existing burner rig test data. For failure mode B, the crack growth rate along the topcoat/TGO interface was calculated using the experimentally measured average interfacial fracture toughness.