No description available.

ESD, the discharge of electrostatically generated charges into an IC, is one of the most important reliability problems for ultra-scaled devices. This electrostatic charge can generate voltages of up to tens of kilovolts. These very high voltages can generate very high electric fields and currents across semiconductor devices, which may result in dielectric damage or melting of semiconductors and contacts. It has been reported that up to 70% of IC failures are caused by ESD. Therefore, it’s necessary to design a protection circuit for each pin that discharges the ESD energy to the ground. As the devices are continuously scaling down, while ESD energy remains the same, they become more vulnerable to ESD stress. This higher susceptibility to ESD damage is due to thinner gate oxides and shallower junctions. Furthermore, higher operating frequency of the scaled technologies enforces lower parasitic capacitance of the ESD protection circuits. As a result, increasing the robustness of the ESD protection circuits with minimum additional parasitic capacitance is the main challenge in state of the art CMOS processes. Providing a complete ESD immunity for any circuit involves the design of proper protection circuits for I/O pins in addition to an ESD clamp between power supply pins. In this research both of these aspects are investigated and optimized solutions for them are reported. As Silicon Controlled Rectifier (SCR) has the highest ESD protection level per unit area, ESD protection for I/O pins is provided by optimizing the first breakdown voltage and latch-up immunity of SCR family devices. The triggering voltage of SCR is reduced by a new implementation of gate-substrate triggering technique. Furthermore, a new device based on SCR with internal darlington pair is introduced that can provide ESD protection with very small parasitic capacitance. Besides reducing triggering voltage, latch-up immunity of SCR devices is improved using two novel techniques to increase the holding voltage and the holding current. ESD protection between power rails is provided with transient clamps in which the triggering circuit keeps the clamp “on” during the ESD event. In this research, two new clamps are reported that enhance the triggering circuit of the clamp. The first method uses a CMOS thyristor element to provide enough delay time while the second method uses a flip flop to latch the clamp into “on” state at the ESD event. Moreover, the stability of transient clamps is analyzed and it’s been shown that the two proposed clamps have the highest stability compared to other state of the art ESD clamps. Finally, in order to investigate the impact of ESD protection circuits on high speed applications a current mode logic (CML) driver is designed in 0.13μm CMOS technology. The protection for this driver is provided using both MOS-based and SCR-based protection methods. Measurement results show that, compared to MOS-based protection, SCR-based protection has less impact on the driver performance due to its lower parasitic capacitance.

ESD, the discharge of electrostatically generated charges into an IC, is one of the most important reliability problems for ultra-scaled devices. This electrostatic charge can generate voltages of up to tens of kilovolts. These very high voltages can generate very high electric fields and currents across semiconductor devices, which may result in dielectric damage or melting of semiconductors and contacts. It has been reported that up to 70% of IC failures are caused by ESD. Therefore, it’s necessary to design a protection circuit for each pin that discharges the ESD energy to the ground. As the devices are continuously scaling down, while ESD energy remains the same, they become more vulnerable to ESD stress. This higher susceptibility to ESD damage is due to thinner gate oxides and shallower junctions. Furthermore, higher operating frequency of the scaled technologies enforces lower parasitic capacitance of the ESD protection circuits. As a result, increasing the robustness of the ESD protection circuits with minimum additional parasitic capacitance is the main challenge in state of the art CMOS processes. Providing a complete ESD immunity for any circuit involves the design of proper protection circuits for I/O pins in addition to an ESD clamp between power supply pins. In this research both of these aspects are investigated and optimized solutions for them are reported. As Silicon Controlled Rectifier (SCR) has the highest ESD protection level per unit area, ESD protection for I/O pins is provided by optimizing the first breakdown voltage and latch-up immunity of SCR family devices. The triggering voltage of SCR is reduced by a new implementation of gate-substrate triggering technique. Furthermore, a new device based on SCR with internal darlington pair is introduced that can provide ESD protection with very small parasitic capacitance. Besides reducing triggering voltage, latch-up immunity of SCR devices is improved using two novel techniques to increase the holding voltage and the holding current. ESD protection between power rails is provided with transient clamps in which the triggering circuit keeps the clamp “on” during the ESD event. In this research, two new clamps are reported that enhance the triggering circuit of the clamp. The first method uses a CMOS thyristor element to provide enough delay time while the second method uses a flip flop to latch the clamp into “on” state at the ESD event. Moreover, the stability of transient clamps is analyzed and it’s been shown that the two proposed clamps have the highest stability compared to other state of the art ESD clamps. Finally, in order to investigate the impact of ESD protection circuits on high speed applications a current mode logic (CML) driver is designed in 0.13μm CMOS technology. The protection for this driver is provided using both MOS-based and SCR-based protection methods. Measurement results show that, compared to MOS-based protection, SCR-based protection has less impact on the driver performance due to its lower parasitic capacitance.

Electrical insulation under high voltage can eventually fail, causing critical damage to electronics. Such electrostatic discharge (ESD) is the primary source of anomalies or failures on spacecraft due to charged particles from the Sun or planetary radiation belts accumulating in spacecraft insulators. Highvoltage direct current power distribution is another example of a growing industry that needs to estimate the operational lifetime of electrical insulation. My research compares laboratory tests of ESD events in common insulating materials to a physics-based model of breakdown. This model of breakdown is based on the approximation that there are two primary types of defects in structurally amorphous insulators. One of the two defect modes can switch on and off depending on the material temperature. This dual-defect model can be used to explain both ESD and less-destructive transient partial discharges. I show that the results of ESD tests agree reasonably well with the dual defect model. I also show that transient partial discharges, which are usually ignored during ESD tests, are closely related to the probability of catastrophic ESD occurring. Since many partial discharges are typically seen during one ESD test, this relationship suggests that the measurements of partial discharges could accelerate the testing needed to characterize the likelihood of ESD in insulating materials.

The contious reduction in size and work voltage of the new generation integrated circuits (ICs) requires the reducction of the thickness of the different layers that make up (especially the gate oxides and levels of isolation between conductors), in order to increase its density and speed of integration, reducing its energy consumption. However, these improvements involve an increase in their sensitivity to external perturbations such as fluctuations in the electricity network, capacitive coupling or electrostatic discharge (ESD). Although there is a wide range of electronic devices designed to protect ICs from such disturbances avoiding destruction (Zener diodes, thyristors, etc.), The continuous reduction of voltage operation and increasing the frequency of work has required a major research effort to adapt the protective devices to the new conditions of operation. The main features that should satisfy any device designed to protect an electronic system are: fast response, low parasitic capacity, driving in low resistance, high absorption capacity of current, low leakage current in reverse, minimum size, low cost, should not interfere in the normal mode of operation of the system that protects and must maintain unchanged its electrical characteristics over time. In high voltage applications, Zener diodes and thyristors are the most used, both in format as a discreet way to the monolithic IC, for protection against ESD phenomena. However, new generations of ICs for mobile applications (portable computers, telecommunications, remote control systems, etc.) Require devices capable of working at low voltage and low energy consumption (in order to maximize the life of batteries ). Under these conditions, the protection of traditional elements are not optimal, so that further protection devices with low voltage and low shooting leakage current in his block state. In this situation, the use of new protective structures based on a process of rupture by emptying (punch-through) improves the characteristics of those based on a break by avalanche (base of the traditional components). Thus, this study aims to analyze, optimize, design and produce new elements of protection by breaking with punch-through, known as Transient Voltage Suppressors (TVS), which improve the performance of Zener diodes in applications from low tension (less than 3 V). Thus, Chapter 1 describes the main electric perturbation and sources that originated, along with a description of its effect on the CIs. It also provides a description of the different existing devices suppressors, with special emphasis on TVS, the main topic for this work. In Chapter 2 presents a study of the vertical TVS based in the punch-through effect, which analyzes the electrical characteristics of its two configurations (TVS 3 layers, TVS 4 layers). It also presents the theoretical model of rupture developed for this type of structures as well as the verification of it through numerical simulations and experimental data. Chapter 3 deals with the design, fabrication and characterization of vertical TVS. We show the technological processes done and the improvements are detailed, demonstrating the superiority of TVS 4 layers respect to the TVS 3 layers and Zener diodes. Chapter 4 presents the first study published on lateral punch-through TVS devices intended to be integrated with the circuitry to protect. The study was conducted for different configurations proposed in technology Bulk Silicon, compared among themselves and choose the configuration that shows better characteristics. This chapter also presents a novel way of using the field plate to reduce the breakdown voltage into the lateral TVS. Finally, and as a line of the future, assessing the feasibility of integrating lateral TVS devices in SOI (Silicon-On-Insulator) substrates. Finally, Chapter 5 shows the manufacturing of lateral TVS. Details the technological process, the design of masks, clean room manufacturing in the characterization and finally, whether technological, using techniques of Reverse Engineering, as electric.

La protection contre les décharges électrostatiques (ESD) est un fait necessaire dans chaque circuit intégré. Elle se fait par le déploiement sur la puce d'un réseau de dispositifs spéciaux, à côtés des éléments fonctionnels. La demande pour des améliorations en continu dans la conception et la simulation de l'ESD apporte le besoin de modèles nouveaux et plus précises. La SCR (« Silicon Controlled Rectifier ») est l'un des dispositifs les plus efficaces de protection contre l'ESD. Un nouveau modèle électrique, qui peut être utilisé pour évaluer les structures de protection complexe dont il fait partie, a été développé au cours de cette thèse. Construit avec une forte relation entre les phénomènes physiques et ses équations, il a été parametrisé geometriquement, offrant la possibilité d'adapter et d'optimiser le dispositif selon le niveau de protection nécessaire. Par ailleurs, une étude à haute fréquence sur le SCR et la diode de protection ESD a été réalisé, conduisant à un modèle capable de prédire l'impact de ces dispositifs ont sur le circuit protégé. / Electrostatic discharge (ESD) protection is a must in every integrated circuit. It is done by deploying a network of special devices on-chip, alongside the functional elements. The demand for continuously improvements in ESD design and simulations brings the need of new and more accurate scalable models. The SCR (silicon controlled rectifier) is one of the most efficient ESD protection devices. A new electrical model, that can be used to evaluate the complex protection structures of which it is part of, was developed during this thesis. Built with a strong relation between the physical phenomena and its equations, it was rendered scalable, offering the possibility of tailoring and optimizing the device according to the needed protection level. Moreover, a high-frequency study on the SCR and the ESD protection diode was carried out, leading to a model able to predict the impact these devices have on the protected circuit.

Optical beam induced current (OBIC) mapping has found wide-spread applications in characterizing semiconductor devices and integrated circuitry. In this study, we have used a two-photon scanning microscope to investigate InGaN light emitting diodes (LED). The defects induced by electrostatic discharge (ESD) can be clearly identified by DC-OBIC images. Additionally, we have combined an E-O modulator and a high frequency phase sensitive lock-in amplifier to conduct time-resolved study on the dynamical properties of the LEDs. The defects also exhibit different delay time when compared with the normal parts.

In this thesis, a system to locate an electrostatic discharge (ESD) event within an electronic device has been developed. ESD can cause a device to fail legally required radiated emissions limits as well as disrupt intended operation. The system used a fast oscilloscope with four channels, each channel attached to a high frequency near-field antenna. These antennas were placed at known locations in three dimensional space to measure the fields radiated from the ESD event. A Time-Difference-of-Arrival technique was used to calculate the location of the ESD event. Quick determination of the ESD event location provides developers with a tool that saves them time and money by eliminating the time-consuming and tedious method of general ESD mitigation within a product.

La miniaturisation des circuits intégrés se poursuit de nos jours avec le développement de technologies toujours plus fines et denses. Elle permet une intégration des circuits toujours plus massive, avec des performances plus élevées et une réduction des coûts de production. La réduction de taille des circuits s'accompagne aussi d'une augmentation de leur sensibilité électrique. L'électronique automobile est un acteur majeur dans la nouvelle tendance des véhicules autonomes. Ce type d'application a besoin d'analyser des données et d'appliquer des actions sur le véhicule en temps réel. L'objectif à terme est d'améliorer la sécurité des usagers. Il est donc vital de garantir que ces modules électroniques pourront effectuer leurs tâches correctement malgré toutes les perturbations auxquelles ils seront exposés. Néanmoins, l'environnement automobile est particulièrement sévère pour l'électronique. Parmi tous les stress rencontrés, les décharges électrostatiques (ESD - Electrostatic Discharge) sont une importante source d'agression électrique. Ce type d'évènement très bref est suffisamment violent pour détruire des composants électroniques ou les perturber pendant leur fonctionnement. Les recherches présentées ici se concentrent sur l'analyse des défaillances fonctionnelles. À cause des ESD, des fonctions électroniques peuvent cesser temporairement d'être opérantes. Des méthodes d'analyse et de prédiction sont requises au niveau-circuit intégré afin de détecter des points de faiblesses susceptibles de générer des fautes fonctionnelles pendant l'exposition à un stress électrostatique. Différentes approches ont été proposées dans ce but. Une méthode hiérarchique de modélisation a été mise au point afin d'être capable de reproduire la forme d'onde ESD jusqu'à l'entrée du circuit intégré. Avec cette approche, chaque élément du système est modélisé individuellement puis son modèle ajouté au schéma complet. Un cas d'étude réaliste de défaillance fonctionnelle d'un circuit intégré a été analysé à l'aide d'outils de simulation. Afin d'obtenir plus de données sur cette faute, une puce de test a été développée, contenant des structures de surveillance et de mesure directement intégrées dans la puce. La dernière partie de ce travail de recherche est concentrée sur le développement de méthodes d'analyse dans le but d'identifier efficacement des fautes par simulation. Une des techniques développées consiste à modéliser chaque bloc d'une fonction individuellement puis permet de chaîner ces modèles afin de déterminer la robustesse de la fonction complète. La deuxième méthode tente de construire un modèle équivalent dit boite-noire d'une fonction de haut-niveau d'un circuit intégré. Ces travaux de recherche ont mené à la mise au point de prototypes matériels et logiciels et à la mise en évidence de points bloquants qui pourront constituer une base pour de futurs travaux. / Miniaturization of electronic circuits continues nowadays with the more recent technology nodes being applied to diverse fields of application such as automotive. Very dense and small integrated circuits are interesting for economic reasons, because they are cheaper to manufacture in mass and can pack more functionalities with elevated performances. The counterpart of size reduction is integrated circuits becoming more fragile electrically. In the automotive world, the new trend of fully autonomous driving is seeing tremendous progress recently. Autonomous vehicles must take decisions and perform critical actions such as braking or steering the wheel. Those decisions are taken by electronic modules, that have now very high responsibilities with regards of our safety. It is important to ensure that those modules will operate no matter the kind of disturbances they can be exposed to. The automotive world is a quite harsh environment for electronic systems. A major source of electrical stress is called the Electrostatic Discharge (ESD). It is a very sudden flow of electricity of large amplitude capable of destroying electronic components, or disturb them during their normal operation. This research focuses on functional failures where functionality can be temporarily lost after an ESD with various impact on the vehicle. To guarantee before manufacturing that a module and its components will perform their duty correctly, new analysis and prediction methods are required against soft-failures caused by electrostatic discharges. In this research, different approaches have been explored and proposed towards that goal. First, a modelling method for reproducing the ESD waveforms from the test generator up to the integrated circuit input is presented. It is based on a hierarchical approach where each element of the system is modelled individually, then added to the complete setup model. A practical case of functional failure at silicon-level is analyzed using simulation tools. To acquire more data on this fault, a testchip has been designed. It contains on-chip monitoring structures to measure voltage and current, and monitor function behavior directly at silicon-level. The last part of this research details different analysis methods developed for identifying efficiently functional weaknesses. The methods rely heavily on simulation tools, and prototypes have been implemented to prove the initial concepts. The first method models each function inside the chip individually, using behavioral models, then enables to connect the models together to deduce the full function's robustness. It enables hierarchical analysis of complex integrated circuit designs, to identify potential weak spots inside the circuit that could require more shielding or protection. The second method is focused on constructing equivalent electrical black box models of integrated circuit functions. The goal is to model the IC with a behavioral, black-box model capable of reproducing waveforms in powered conditions during the ESD. In summary, this research work has led to the development of several hardware and software prototypes. It has also highlighted important modelling challenges to solve in future works to achieve better functional robustness against electrostatic discharges.

Electrostatic Discharges (ESD) is a significant hazard to electronic components and systems. Based on a specific process technology, a given circuit application requires a customized ESD consideration that meets all the requirements such as the core circuit's operating condition, maximum accepted leakage current, breakdown conditions for the process and overall device sizes. In every several years, there will be a new process technology becomes mature, and most of those new technology requires custom design of effective ESD protection solution. And usually the design window will shrinks due to the evolving of the technology becomes smaller and smaller. The ESD related failure is a major IC reliability concern and results in a loss of millions dollars each year in the semiconductor industry. To emulate the real word stress condition, several ESD stress models and test methods have been developed. The basic ESD models are Human Body model (HBM), Machine Mode (MM), and Charge Device Model (CDM). For the system-level ESD robustness, it is defined by different standards and specifications than component-level ESD requirements. International Electrotechnical Commission (IEC) 61000-4-2 has been used for the product and the Human Metal Model (HMM) has been used for the system at the wafer level. Increasingly stringent design specifications are forcing original equipment manufacturers (OEMs) to minimize the number of off-chip components. This is the case in emerging multifunction mobile, industrial, automotive and healthcare applications. It requires a high level of ESD robustness and the integrated circuit (IC) level, while finding ways to streamline the ESD characterization during early development cycle. To enable predicting the ESD performance of IC's pins that are directly exposed to a system-level stress condition, a new the human metal model (HMM) test model has been introduced. In this work, a new testing methodology for product-level HMM characterization is introduced. This testing framework allows for consistently identifying ESD-induced failures in a product, substantially simplifying the testing process, and significantly reducing the product evaluation time during development cycle. It helps eliminates the potential inaccuracy provided by the conventional characterization methodology. For verification purposes, this method has been applied to detect the failures of two different products. Addition to the exploration of new characterization methodology that provides better accuracy, we also have looked into the protection devices itself. ICs for emerging high performance precision data acquisition and transceivers in industrial, automotive and wireless infrastructure applications require effective and ESD protection solutions. These circuits, with relatively high operating voltages at the Input/Output (I/O) pins, are increasingly being designed in low voltage Complementary Metal-Oxide-Semiconductor (CMOS) technologies to meet the requirements of low cost and large scale integration. A new dual-polarity SCR optimized for high bidirectional blocking voltages, high trigger current and low capacitance is realized in a sub 3-V, 180-nm CMOS process. This ESD device is designed for a specific application where the operating voltage at the I/O is larger than that of the core circuit. For instance, protecting high voltage swing I/Os in CMOS data acquisition system (DAS) applications. In this reference application, an array of thin film resistors voltage divider is directly connected to the interface pin, reducing the maximum voltage that is obtained at the core device input down to ± 1-5 V. Its ESD characteristics, including the trigger voltage and failure current, are compared against those of a typical CMOS-based SCR. Then, we have looked into the ESD protection designs into more advanced technology, the 28-nm CMOS. An ESD protection design builds on the multiple discharge-paths ESD cell concept and focuses the attention on the detailed design, optimization and realization of the in-situ ESD protection cell for IO pins with variable operation voltages. By introducing different device configurations fabricated in a 28-nm CMOS process, a greater flexibility in the design options and design trade-offs can be obtained in the proposed topology, thus achieving a higher integration and smaller cell size definition for multi-voltage compatibility interface ESD protection applications. This device is optimized for low capacitance and synthesized with the circuit IO components for in-situ ESD protection in communication interface applications developed in a 28-nm, high-k, and metal-gate CMOS technology. ESD devices have been used in different types of applications and also at different environment conditions, such as high temperature. At the last section of this research work, we have performed an investigation of several different ESD devices' performance under various temperature conditions. And it has been shown that the variations of the device structure can results different ESD performance, and some devices can be used at the high temperature and some cannot. And this investigation also brings up a potential threat to the current ESD protection devices that they might be very vulnerable to the latch-up issue at the higher temperature range.