Electrical insulation under high voltage can eventually fail, causing critical damage to electronics. Such electrostatic discharge (ESD) is the primary source of anomalies or failures on spacecraft due to charged particles from the Sun or planetary radiation belts accumulating in spacecraft insulators. Highvoltage direct current power distribution is another example of a growing industry that needs to estimate the operational lifetime of electrical insulation. My research compares laboratory tests of ESD events in common insulating materials to a physics-based model of breakdown. This model of breakdown is based on the approximation that there are two primary types of defects in structurally amorphous insulators. One of the two defect modes can switch on and off depending on the material temperature. This dual-defect model can be used to explain both ESD and less-destructive transient partial discharges. I show that the results of ESD tests agree reasonably well with the dual defect model. I also show that transient partial discharges, which are usually ignored during ESD tests, are closely related to the probability of catastrophic ESD occurring. Since many partial discharges are typically seen during one ESD test, this relationship suggests that the measurements of partial discharges could accelerate the testing needed to characterize the likelihood of ESD in insulating materials.

Oxide dielectric breakdown is an old problem that has been studied over decades. It causes power dissipations and irreversible damage to the electronic devices. The aggressive downscaling of the device size exponentially increases the leakage current density, which also raises the risk of dielectric breakdown. It has been proposed that point defects, current leakages, impurity diffusions, etc. all contribute to the change of oxide chemical composition and ultimately lead to the dielectric breakdown. However, the conclusive cause and a clear understanding of the entire process of dielectric breakdown are still under debate. In this research, the electronic structure at metal/oxide interfaces is studied using first-principle calculations within the framework of Density Functional Theory (DFT) to investigate any possible key signature that would trigger the dielectric breakdown. A classical band alignment method, the Van de Walle method, is applied to the case study of the Al/crystal-SiO2 (Al/c-SiO2) interface. Point defects, such as oxygen vacancy (VO) and hydrogen impurity (IH), are introduced into the Al/c-SiO2 interface to study the effects on band offset and electronic structure caused by point defects at metal/oxide interfaces. It is shown that the bonding chemistry at metal/oxide interfaces, which is mainly ionic bond, polarizes the interface. It results in many interface effects such as the interface dipole, built-in voltage, band bending, etc. Charge density analysis also indicates that the interface can localize charge due to such ionic bonding. It is also found that VO at the interface traps metal electrons which closes the open -sp3 orbital. The analysis on local potential shows that the metal potential penetrates through a few layers of oxide starting from the interface, which metalizes the interfacial region and induces unoccupied states in the oxide band gap. In addition, it is shown that higher oxygen content at metal/oxide interfaces minimizes such metal potential invasion. In addition, an oxygen vacancy is created at multiple sites through the Al/c-SiO2 and Al/a-SiO2 interface systems, separately. The oxygen local pressure is also calculated before its removal using Quantum Stress Density theory. Correlations among electronic structure, stress density, and vacancy formation energy are found, which provide informative insights into the defect generation controlling and dielectric breakdown analysis. A new band alignment approach based on the projection of plane-waves (PWs) into the space-dependent atomic orbital (LCAO) basis is presented and tested against classical band offset methods -- the Van de Walle method. It is found that the new band alignment approach can provide a quantitative and reliable band alignment and can be applied to the heterojunctions consisting of amorphous materials. The new band alignment approach reveals the real-space dependency of the electronic structure at interfaces. In addition, it includes all interface effects, such as the interface dipole, built-in voltage, virtual oxide thinning, and band deformation, which cannot be derived using classical band offset methods. This new band alignment approach is applied to the case study of both the Al/amorphous-SiO2 (Al/a-SiO2) interface and the Al/c-SiO2. We have found that at extremely low dimensions, the reduction of the insulator character due to the virtual oxide thinning is a pure quantum effect. I highlight that the quantum tunneling current leakage is more critical than the decrease of the potential barrier height on the failure of the devices. / PHD

De nos jours, l'essor des produits électroniques nomades requièrent une capacité de stockage de données croissante et imposent la fabrication de composants mémoire performants, denses et fiables. Cela implique une grande robustesse des cellules mémoires élémentaires dont les dimensions caractéristiques sont régulièrement réduites. L'objectif principal de la thèse est d'appréhender les mécanismes de claquage d'oxydes minces voire ultraminces intégrés dans des empilements métal/oxyde/semiconducteur. Un intérêt particulier a été porté à la croissance d'îlots cristallins épitaxiés se formant lors de certaines sollicitations électriques et associée aux mécanismes de DBIE (Dielectric Breakdown Induced Epitaxy). L'étude des différents dispositifs (cellules mémoires à grille continue ou discrète, transistors, condensateur) a permis de proposer des corrélations entre la défaillance électrique de ces dispositifs et les défauts microstructuraux générés. Ce travail a été réalisé selon une méthodologie intégrant (i) la sollicitation électrique ; (ii) une préparation d'échantillons adaptée ; (iii) l'identification, l'observation et la caractérisation des défauts par microscopie électronique en transmission (TEM). L'ensemble des études menées a permis d'isoler deux paramètres électriques principaux ayant un rôle prépondérant sur la formation d'îlots de silicium épitaxiés, en lien avec le mécanisme de DBIE : la charge injectée et le courant de compliance. Ces deux paramètres apparaissent comme des facteurs limitant l'emballement thermique qui conduit, en général, à un claquage diélectrique franc de l'oxyde et semblent, par conséquent, retarder la défaillance irréversible d'un dispositif. / Nowadays, the microelectronic industry had to take up ambitious challenges to satisfy the strong economic demand because of the mobile electronic products booming like smartphones, tablets, or more recently "phablets". These high added value products requires the growth of data storage capacity and, subsequently, to produce high-performance, dense and reliable components. That implies a great cell memories robustness whose critical dimensions are regularly reduced. In this context, the thesis issue is to better understand the breakdown mechanisms of the thin and ultra-thin oxides embedded in metal/oxide/semiconductor stacks. Actually, epitaxial growth of crystalline silicon hillocks was pinpointed. These hillocks grown under electrical stresses and were associated to DBIE mechanisms (Dielectric Breakdown Induced Epitaxy). Device studies allowed to correlate electrical stress conditions and microstructural defects thanks to a 3-steps methodology : (i) electrical stresses leading to microstructural defects ; (ii) sample preparation including defect localization and extraction ; (iii) identification, observation and characterization of defects by transmission electron microscopy (TEM). Two main electrical parameters were identified with factors responsible for hillocks growth linked to DBIE : the injected charge and the compliance current. These parameters seem to limit the thermal runaway inducing hard breakdown. Consequently, it is possible that delays the irreversible device degradation. In addition, hillocks seem to grow preferentially under polysilicon grain boundaries over the SiO2/Si stacks.

Student Number : 9803381J - MSc Dissertation - Faculty of Engineering and the Built Environment / Although pulsed power has been used in many parts of the world over the last few decades to initiate high-voltage discharges through rock, no systematic test work on South African ore bodies and related rock types has been done so far. As part of CSIR Miningtek’s integrated approach of combining underground comminution with a novel Tore© hydrotransport system, which has been shown to operate well with coarse particles up to 10 mm, various rock types were fragmented in single discharge mode under laboratory conditions. The work was conducted at the University of the Witwatersrand’s high-voltage laboratory with a custom-designed test rig. The rig configuration was based on a critical review and analysis of the literature and on assessments of existing test facilities elsewhere. Core samples with diameters ranging from 16 to 48 mm were cut from test specimens with thicknesses ranging from 8 to 48 mm. Rock types included Ventersdorp Contact Reef, Carbon Leader, Elsburg Formation, UG2 and Merensky, as well as pure quartz, shales, lava and dykes. A six-stage Marx generator provided a voltage rise time of 2 000 kV/μs to create a discharge through the rock, in preference to a discharge through the surrounding water, which acts as an insulator at ramp-up times faster than 0,5 μs. High-speed photography, and an analysis of the voltage and current signals for various rock types and for water alone, were used to quantify the potential benefits of rock breaking by electric discharge. It was found that some Kimberlite specimens and mineralised gold-bearing reefs were much easier to fragment than hanging wall or footwall material. Merensky reef appeared to be more susceptible than the less brittle UG2 material. A correlation was derived between the dynamic resistivity of various rock types, measured at 16 MHz excitation frequency, and the electrical breakdown strength at which discharge took place. The fragments created had a more cubical shape than would be created by conventional impact crushing. However, the high voltage requirements of about 30 to 35 kV per millimetre of rock thickness would necessitate not only efficient mechanical and electrical contact between the electrodes and the rock, but also considerable safety features for underground installations. The clearly identified, preferential fracturing of reef rock types, compared with the hanging or footwall materials, suggests that the greater benefit of electric rock breaking may lie in primary rock breaking as a mining method, rather than in secondary comminution of broken rock to enable hydraulic transportation by pipeline to surface.

The 21st century marks the defining point of human history in terms of technological advancement. In 2014, we were at the edge of acquiring a complete understanding of the fundamental construct to all life forms. The capability to manipulate and recreate lives as desired will soon be at our hands and will eventually lead to the redefinition of life and humanity. This brave new world, for better or worse, will be stitched together by scientific breakthroughs in many disciplines. Nanopore fluidic system – and microfluidic in general – might be one of the key puzzles towards the future. It is seen as a likely candidate for the next generation of rapid and low-cost genetic sequencing technology, which will allow us to gain thorough insight into the genetic code of every living organism on earth. It can also have the capability to individually detect and manipulate virtually any biological molecules, possibly allowing it to be a universal diagnostic tool or a bio-molecule synthesiser. The future of nanopore fluidic system is prosperous, but the difficulties are equally challenging. Currently, both biological and solid-state nanopores are non-trivial to create. For instance, a small solid-state nanopore can only be fabricated with expansive machinery in a low-yield, low-throughput manner. To overcome this challenge, a new set of methods involving high electric field to fabricate and enlarge a solid-state nanopore has been developed. It was found that a nanopore, when subjected to a high electric field, can be enlarged in angstrom increments and cleared of unidentified obstructions that cause low-frequency ionic current fluctuations. It was also found that an intact solid-state membrane, when subjected to a high electric field for a period of time, can leave a single nanopore imprinted onto it. The process of creation is best describe as a dielectric breakdown event and can be modeled by the percolation theory for dielectric breakdown. The resulting nanopores are cylindrical in shape and are shown to be equally capable of single molecule sensing compare to pores created by other methods. To accommodate future nanopore designs and applications and to examine the scope of applicability of the new fabrication approach, more advanced nanopore devices were created on some dual-layer solid-state membranes comprising of a metallic and a dielectric layer. Experiments indicated that the method could indeed create nanopore on such advanced membranes. It was further shown that the metallic layer receded further than the dielectric layer, forming a hollow conical shape at the opening of the dielectric nanopore. Such metalized bi-layer nanopore system was found to interact strongly with short single stranded DNA molecules, resulting in prolonged DNA translocation time. A simple picture of the mechanism was proposed to explain the observation. Lastly, to extend the limit of the new fabrication approach, I attempted to fabricate nanopore on complex multi-layer membranes involving a graphene film sandwiched in several dielectric materials. It was found that the quality of the graphene film and the transfer method were vital to the success of this project. Nevertheless, preliminary results indicated that the new method could create a nanopore through this complex multi-layer membrane. The new method to fabricate and tune both simple and complex nanopores is amongst the simplest, the least costly and the most efficient one that one can imagine. The research work has already sparked a dramatic increase in scientific throughput in our laboratory and other laboratories we had collaboration with. It fueled more than a dozen projects and involved close to a thousand nanopores in total. Such projects are far from possible if they were to rely on conventional fabrication methods. However, these are insignificant if we consider the new method is simple enough that, for the very first time, general public can easily access nanofabrication and single-molecule manipulation technology. The liberation of nanotechnology to the general public symbolically marks the beginning of a brave new world.

This dissertation explores CMOS RF design and reliability for portable wireless receivers. The objective behind this research is to achieve an increase in integration level, and gain more understanding for RF reliability. The fields covered include device, circuit and system. What is under investigation is a multi-band multi-mode receiver with GSM, DCS-1800 and CDMA compatibility. To my understanding, GSM and CDMA dual-mode mobile phones are progressively investigated in industries, and few commercial products are available. The receiver adopts direct conversion architecture. Some improved circuit design methods are proposed, for example, for low noise amplifier (LNA). Except for band filters, local oscillators, and analog-digital converters which are usually implemented by COTS SAW filters and ICs, all the remaining blocks such as switch, LNA, mixer, and local oscillator are designed in MOSIS TSMC 0.35[micro]m technology in one chip. Meanwhile, this work discusses related circuit reliability issues, which are gaining more and more attention. Breakdown (BD) and hot carrier (HC) effects are important issues in semiconductor industry. Soft-breakdown (SBD) and HC effects on device and RF performance has been reported. Hard-breakdown (HBD) effects on digital circuits have also been investigated. This work uniquely address HBD effects on the RF device and circuit performance, taking low noise amplifier and power amplifier as targets.

Made available in DSpace on 2017-07-21T20:43:48Z (GMT). No. of bitstreams: 1 Charles Betuel Mansende Mvumbi.pdf: 3357827 bytes, checksum: 822a91a949448c4769ce680ef684f74d (MD5) Previous issue date: 2016-01-29 / The ceramic porcelains are produced from natural raw materials (silica, feldspar and kaolin). In some applications other materials are added to increase the mechanical and dielectric strength. They are used in the manufacture of several products. Therefore, they are very studied and have been developed for long time. In this work, porcelains with different compositions were characterized and submitted to fragmentation by mechanical disruption in a ballistic impact testing. Generally the mechanical disruption in the materials produces a power dissipation forming cracks and fracture surfaces having an irregular geometry. The main objective of this work was to characterize the microstructure and the fractal fracture surface in porcelains. For comparison, the impact tests were also performed on commercial glass and acrylic. The evaluation of the fracture surface and the fractal dimension of rupture was performed by analyzing the fraction of the fragments as a function of the probability of fracture. The samples were prepared in the form of cylindrical disks with a thickness and fixed diameters. Mechanical impact test was made on the center of the disks for different materials, maintaining the same test conditions. The results of the size and mass of the fragments were obtained as a function of the impact energy, thickness, diameter and kind of material. Thus, it was possible to obtain a correlation between the test conditions and the composition of the material with the fractal pattern breakage. It has been found that the compositions used in porcelain, has a fracture toughness which is between the glass and acrylic. A correlation between strength properties to the patterns of formed crack was made. It was noticed that the number, the shape of cracks and the branches form a pattern that is associated with the impact energy and material type. / As porcelanas são cerâmicas produzidas a partir de matérias primas naturais (sílica, feldspato e caulim). Em algumas aplicações são adicionadas outras matérias primas para o aumento da resistência mecânica e dielétrica. Elas são usadas na fabricação de variados produtos. Portanto, elas são muito estudadas e vêm sendo desenvolvidas há muito tempo. Neste trabalho, porcelanas com diferentes composições foram caracterizadas e submetidas à fragmentação por ruptura mecânica em um ensaio de impacto balístico. A ruptura mecânica nos materiais em geral produz uma dissipação de energia formando trincas e superfícies de fratura que tem uma geometria irregular. O principal objetivo deste trabalho foi a caracterização da microestrutura e a caracterização fractal da superfície de fratura de porcelanas. Para comparação, os ensaios de impacto também foram feitos em vidro e acrílico comercial. A avaliação da superfície de fratura e da dimensão fractal de ruptura foi feita pela análise da fração de fragmentos em função da probabilidade de fratura. Os corpos de prova foram preparados na forma de discos cilíndricos, com espessura e diâmetros fixos. O ensaio de impacto mecânico foi feito sobre o centro dos discos, para os diferentes materiais, mantendo-se as mesmas condições de ensaios. Os resultados, do tamanho e massa dos fragmentos, foram obtidos em função da energia, espessura, diâmetro e do tipo de material. Desta forma, foi possível obter uma correlação entre as condições de ensaio e a composição do material com o padrão de ruptura fractal. Verificou-se que a porcelana nas composições usadas possui uma tenacidade à fratura que se situa entre a do vidro a do acrílico. Finalmente foi feita uma correlação entre as propriedades de resistência mecânica com os padrões de trinca formado. Percebeu-se que o número, a forma das trincas e as ramificações formam um padrão que está relacionado com a energia de impacto e o tipo de material.

Neste trabalho, investigou-se capacitores MOS fabricados sobre superfícies irregulares contendo formas retangulares periódicas com 100 nm de altura, obtidas a partir de corrosão por plasma localizadas. Os óxidos de porta com 4,5 nm de espessura foram crescidos em ambientes ultrapuros de O2 ou pirogênico a fim de comparar a uniformidade de cobertura sobre os degraus verticais dos perfis retangulares. Foi mostrado que a oxidação pirogênica ou convencional na temperatura de 850 ºC permite obter óxidos de porta sobre degraus com altura de 100nm com baixa corrente de fuga e alto campo de ruptura. Esse comportamento pode ser interpretado como óxidos de porta perfeitamente amoldados sobre os degraus de 100nm de altura. O impacto deste resultado é agora a possibilidade de implementar óxidos de porta para transistores de porta envolvente e FinFETs. / In this work, it was investigated MOS capacitors fabricated onto periodic rectangular shapes, 100 nm in height, obtained by localized plasma etching onto silicon wafer surfaces. 4.5-nm gate oxide growth was performed in ultrapure dry O2 or pyrogenic environments in order to compare the coverage uniformity at the step edges of rectangular shapes defined onto the silicon surfaces. It was shown that pyrogenic and conventional oxidation at 850 ºC allows one to obtain gate oxides on 100nm-stepped silicon surfaces with low leakage current and high dielectric breakdown field. This behavior can be understood as highly conformal gate oxides over silicon steps with height of 100 nm. The impact of this result is now the feasibility of implementing gate oxides for surrounding gate transistors (SGT\'s) and FinFETs.

Neste trabalho, investigou-se capacitores MOS fabricados sobre superfícies irregulares contendo formas retangulares periódicas com 100 nm de altura, obtidas a partir de corrosão por plasma localizadas. Os óxidos de porta com 4,5 nm de espessura foram crescidos em ambientes ultrapuros de O2 ou pirogênico a fim de comparar a uniformidade de cobertura sobre os degraus verticais dos perfis retangulares. Foi mostrado que a oxidação pirogênica ou convencional na temperatura de 850 ºC permite obter óxidos de porta sobre degraus com altura de 100nm com baixa corrente de fuga e alto campo de ruptura. Esse comportamento pode ser interpretado como óxidos de porta perfeitamente amoldados sobre os degraus de 100nm de altura. O impacto deste resultado é agora a possibilidade de implementar óxidos de porta para transistores de porta envolvente e FinFETs. / In this work, it was investigated MOS capacitors fabricated onto periodic rectangular shapes, 100 nm in height, obtained by localized plasma etching onto silicon wafer surfaces. 4.5-nm gate oxide growth was performed in ultrapure dry O2 or pyrogenic environments in order to compare the coverage uniformity at the step edges of rectangular shapes defined onto the silicon surfaces. It was shown that pyrogenic and conventional oxidation at 850 ºC allows one to obtain gate oxides on 100nm-stepped silicon surfaces with low leakage current and high dielectric breakdown field. This behavior can be understood as highly conformal gate oxides over silicon steps with height of 100 nm. The impact of this result is now the feasibility of implementing gate oxides for surrounding gate transistors (SGT\'s) and FinFETs.

This project investigates the failure of various CMOS circuits as a result of Time Dependent Dielectric Breakdown (TDDB) and explores design techniques to increase the mean time to failure (MTTF) of large-scale circuits. Time Dependent Dielectric Breakdown is a phenomenon where the oxide underneath the gate degrades as a result of the electric field in the material. Currently, there are few well documented design techniques that can increase lifetime, but with a tool chain I created called the MTTF Analyzing Program, or MAP, I was able to test circuits under various conditions in order to identify weak links, discover relationships, and reiterate on my design and see improvements and effects. The tool chain calculates power consumption, performance, temperature, and MTTF for a 'real life' circuit. Electric VLSI, an Electronic Design Automation tool, outputs a Spice file that yields parasitic quantities and spatial dimensions. LTspice, a high performance Spice simulator, was used to calculate the voltage and current data. Finally, I created MAP to monitor the voltage, current, and dimension data and process that in conjunction with HotSpot, a thermal modeling tool, to calculate a MTTF for each MOSFET. Analysis of the data from the software infrastructure showed that transistor sizing played a role in the MTTF. To maximize the MTTF of a transistor in a CMOS inverter, the activity of the pull-up transistor should be balanced with the transistor in the pull-down chain, ensuring the electric fields are balanced across both transistors. While it is impossible to completely balance an arbitrary CMOS circuit's activity for an arbitrary set of input signals, circuits can be intelligently skewed to help maximize the MTTF without increasing power consumption and without sacrificing circuit performance. Consequently, attaining a maximum MTTF does not come at a cost as it is possible to design a circuit with a high MTTF that performs better and uses less power than a circuit with low MTTF.