This thesis focuses on the development of a novel polymer based housing for power thyristor devices typically used in long distance high voltage direct current (HVDC) transmission. Power thyristor devices used in HVDC power conversion stations are typically packaged in a hermetically sealed ceramic housing and have demonstrated an excellent history of reliability and performance. However, to avoid increasing the number of thyristors in future higher powered HVDC schemes thyristors having higher power ratings at 8.5 kV and sizes at 125 mm and 150 mm diameters are sought for implementation to achieve higher transmission ratings of, for example, 4000 A at +/- 800 kV. The main disadvantages of such large ceramic-based packages are higher processing cost and weight whilst robustness is also a concern. To overcome these issues, replacing the current ceramic housing with a polymeric material has been investigated in this project. The advantages it is anticipated such packages will provide include lower cost, less weight, robustness, recyclability, etc. However, some challenges it will also offer are: non-hermeticity i.e. polymers are moisture and gas permeable, potentially more complex manufacturing routes, and different electrical, mechanical and thermal properties compared to ceramic materials. The work presented in this thesis was part of a larger project where these challenges have been addressed by developing and testing a prototype polymeric thyristor housing. The prototype is aimed at demonstrating that polymer packages can deliver performance and reliability comparable to, if not better than, current ceramic packages. In this thesis, it is the package development and reliability related studies that are discussed. Because the housings will experience severe electrical stresses and various thermal excursions during their service life, the electrical and thermo-mechanical behaviour of the polymer housing was studied using finite element analysis to gain an understanding of the effects of various design variables and materials properties on performance and the tradeoffs between performance and manufacturability. From these modelling studies, design guidelines have been established for the future development of polymer housings. On the other hand, to identify the physics-of-failure of the prototype that was manufactured as part of the project, accelerated life tests were performed to study its reliability. The knowledge gained from the polymer prototype development was then applied to the design of a larger 125 mm diameter housing using the Taguchi method of experimental design.

Les mémoires non volatiles intégrées représentent une part importante du marché des semi-conducteurs. Bien qu'il s'adresse à de nombreuses applications différentes, ce type de mémoire fait face à des problèmes pour poursuivre la réduction continue de la résolution des technologies CMOS. En effet, l'introduction récente de high-k et de métal pour la grille des transistors menace la compétitivité de la solution Flash. En conséquence, de nombreuses solutions émergentes sont étudiées. L'Antifuse dans le cadre des mémoires OTP est utilisée pour l'identification de puces, la configuration de circuits, la réparation de système ou le stockage de données sécurisées. La programmation Antifuse repose sur la dégradation de l'oxyde de grille de son condensateur sous haute tension. Des travaux antérieurs ont déjà apporté quelques connaissances sur les mécanismes physiques impliqués sur des technologies à oxyde de grille SiO2. De nouveaux défis découlent de l'introduction des nouveaux matériaux de grille. Un examen complet est nécessaire sur les mécanismes de dégradation des oxydes impliqués dans la programmation Antifuse. L'utilisation intensive de la haute tension suggère également d'étendre notre connaissance sur la fiabilité dans cette gamme de tension. Les états pré et post-claquage de l'oxyde de grille sous des mécanismes à haute tension sont donc étudiés dans ce manuscrit se concentrant sur les technologies CMOS les plus avancées. Une loi en puissance type TDDB a été étendue vers les hautes tensions pour être utilisée comme un modèle de temps de programmation Antifuse. L'extension de la fiabilité TDDB nous donne également un élément clé pour modéliser la durée de vie du transistor de sélection. Des paramètres de programmation tels que l'amplitude de la tension, la compliance du courant ou la température sont également étudiés et leur impact sur le rendement en courant de lecture est abordé. Cette étude nous permet de rétrécir agressivement la surface globale de la cellule sans perte de performance ni de dégradation de la fiabilité. Un processus de caractérisation Antifuse est proposé pour être retravaillé et un modèle de programmation de tension-température-dépendante est inventé. Ce manuscrit a également mis l'accent sur la modélisation de courant de cellule programmée comme la fuite d’un oxyde de grille post-claquage. Un modèle compact MOSFET dégradé est proposé et comparé à l'état de l’art. Un bon accord est trouvé pour s'adapter à la large gamme de caractérisations I (V) de la cellule programmée. L'activation de ce modèle dans un environnement de design nous a permis de simuler la dispersion des distributions de courants de cellules programmées au niveau de la taille du produit à l'aide de runs Monte-Carlo. Enfin, cette thèse s'achève autour d'une étude d'investigation OxRAM comme une solution émergente. En combinant le dispositif Antifuse avec le mécanisme de commutation résistif de l'OxRAM, une solution hybride est proposée en perspective. / Embedded Non Volatile Memories represent a significant part of the semiconductor market. While it addresses many different applications, this type of memory faces issues to keep the CMOS scaling down roadmap. Indeed, the recent introduction of high-k and metal for the CMOS gate is threatening the Flash’s competitiveness. As a consequence many emerging solutions are being. The Antifuse as part of the OTP memories is fully CMOS compliant, Antifuse memories are used for Chip ID, chip configuration, system repairing or secured data storage to say the least. The Antifuse programming relies on the gate oxide breakdown of its capacitor under high voltage. Previous work already brought some knowledge about the physical mechanisms involved but mainly on SiO2 gate oxide technologies. New challenges arise from the introduction of the new gate materials. A full review is needed about the oxide breakdown mechanisms involved in the Antifuse programming. The extensive use of high voltage also suggests to extend our knowledge about reliability within this voltage range. Pre and post gate oxide breakdown under high voltage mechanisms are then deeply investigated in this manuscript focusing on the most advanced CMOS technologies. Fowler Nordheim Tunneling has been confirmed as the main mechanism responsible for the gate oxide leakage conduction under high voltage during the wearout phase even-though defect contribution has been evidenced to mainly contribute under low voltage , e.g. the virgin Antifuse leakage current. A TDDB based power law has been extended toward high voltage to be used as a robust Antifuse programming time model. Extending the TDDB reliability under high electric field also gives us key element to model the selection MOSFET time to failure. Programming parameters such as voltage amplitude, current compliance or temperature are also investigated and their impact on the Read Current Yield are tackled. This study allows us to aggressively shrink the bitcell overall area without losing performance nor degrading the reliability. This study also reveals a worst case scenario for the programming parameters when temperature is very low. As a consequence, the early Antifuse characterization process is proposed to be rework and a programming voltage-temperature-dependent solution is invented. This manuscript also focused on the Antifuse programmed cell current modeling as gate oxide post-breakdown conduction. A remaining MOSFET compact model is proposed and compared to the state of the art. Good agreement is found to fit the wide range of read current. Enabling this model within a CAD environment has allowed us to simulate the Read Current Yield dispersion at product size level using Monte-Carlo runs. Finally, this thesis wraps up around an OxRAM investigation study as a serious emerging eNVM solution. Combining the Antifuse device with the resistive switching mechanism of the OxRAM, a hybrid solution is proposed as a perspective.

Les MOSFET en SiC sont appelées à remplacer les IGBT en Silicium pour des applications de demandant une plus forte vitesse de commutation. Cependant, les MOSFET en SiC ont encore quelques problèmes de fiabilité, tels que la robustesse de la diode interne ou bien la robustesse de l'oxyde de grille. Cette dernière est liée à l’oxyde de grille des composants du type MOSFET. Des instabilités de la tension de seuil sont aussi signalées. Cette thèse aborde ces deux sujets sur des MOSFET commerciaux 1200 V. L'étude de la diode interne met en évidence que les caractéristiques I-V (de la diode intrinsèque) demeurent stables après l'application d'un stress. Cependant, une dérive surprenante de la tension de seuil apparaît. Des tests complémentaires, en stressant le canal à la place de la diode, avec les mêmes contraintes n'ont pas montré de dérive significative de la tension de seuil. Donc, l'application d'un stress en courant quand le composant est en mode d'accumulation semble favoriser l'apparition des instabilités de la tension de seuil. La robustesse de l'oxyde de grille concerne les instabilités de la tension de seuil, mais aussi l'estimation de la durée de vie à des conditions d'opération nominales. Les résultats obtenus montrent que la durée de vie de l'oxyde de grille n'est plus un problème. Pourtant, le suivi du courant de grille pendant les tests ainsi que les caractérisations de la capacité de grille mettent en évidence des translations de la courbe C(V) à cause des phénomènes d’injection des porteurs et de piégeage, mais aussi la possible présence d’ions mobiles. Aussi, une bonne analyse des dégradations et dérives liées à l’oxyde de grille doit être réalisée. / SiC power MOSFETs are called to replace Si IGBT for some medium and high power applications (hundreds of kVA). However, even if crystallographic defects have been drastically reduced, SiC MOSFETs are always concerned by some robustness issues such as the internal diode robustness or the robustness of the gate oxide. The last one especially affects MOSFETs devices and is linked to the apparition of instabilities in the threshold voltage. This thesis focuses on these two issues. The study of the internal diode robustness highlighted that the I-V curve (of the intrinsic diode) remains stable after the application of a current stress in static mode, but also with the DUT placed in a converter with inductive switchings. These are the most stressful conditions. However, a surprising drift in the threshold voltage has been observed when some devices operates under these conditions; in static mode or in a converter. Complementary tests stressing the channel instead of the internal diode in the same temperature and dissipated power, have not resulted in a drift of the threshold voltage. Thus, the application of a current stress when the device is in accumulation regime could favour the apparition of instabilities in the threshold voltage. The study of the gate oxide focus in the instabilities of the threshold voltage, but also on the expected lifetime of the oxide at nominal conditions. Results obtained shown that the expected lifetime (TDDB) of the oxide is no longer a problem. Indeed, tests realized in static mode, but also in a converter under inductive switching conditions resulted in expected lifetimes well above 100 years. However, the monitoring of the gate current during the test and gate capacitance characterizations C(V) highlighted a shift in the capacitance due to carrier injection and trapping phenomena and probably to the presence of mobile-ions. Still regarding the instabilities of the threshold voltage, classic tests resulted in no significant variations of the threshold voltage at 150 _C. However, at 200 _C the drift observed for some manufacturers is higher than +30%. This is unacceptable for high-temperature applications and evidence that the quality of the gate oxide and the SiC=SiO2 interface must continue to be improved, together with the manufacturing methods to minimize the presence of mobile ions in the substrate.

Les progrès rapides de la microélectronique sont liées à la miniaturisation du transistor MOS. Pour limiter les courants de fuite, SiO2 a déjà été remplacé par HfO2.mais de nouveaux diélectriques de grande constante diélectrique (high-k) devront être intégrés pour poursuivre cette progression. Le microscope à force atomique (AFM) en mode Conductive-AFM (C-AFM) est aujourd'hui un outil incontournable pour la caractérisation électrique des diélectriques en couche mince à l'échelle nanométrique. Dans nos travaux, nous avons cherché à étudier les limites du C-AM. Le C-AFM consiste à utiliser une pointe AFM comme électrode supérieure afin de faire des mesures de type I(V) ou des cartographies de courant. Nous avons cherché à identifier le phénomène qui conduit à la dégradation de la couche diélectrique par l'application d'une tension de pointe positive, matérialisée par la déformation de la surface. Nous avons montré qu'il s'agissait d'un effet thermique due à la forte densité de courant, ne s'apparentant pas à la DBIE observée sur dispositif, et pouvant aller jusqu'à la détérioration du substrat à l'interface. Ce phénomène, sans en être la conséquence, est largement favorisé par la présence d'eau. Ceci confirme qu'il est préférable de réaliser les caractérisations électriques sous ultra-vide malgré les contraintes expérimentales. Les études du diélectriques sont ainsi compromises puisque le mode de dégradation est en partie propre à la technique AFM et ne permet pas aisément d'extrapoler le comportement du matériau intégré dans un dispositif. De plus, l'étude statistique la dégradation de la couche (Weibull), couramment utilisée, est affectée par un biais d'interdépendance. De la même façon, la modélisation de la conduction à travers la couche doit être utilisée avec précaution, car la surface du contact électrique pointe-diélectrique demeure un paramètre incertain. La technique de pompage de charges permet de caractériser les pièges à l'interface oxyde/semi- conducteur en les sollicitant par l'application d'une tension de grille périodique. Elle permet d'extraire la densité d'état Dit(E) les sections efficaces de capture (σ(E)), mais ne donne pas d'information sur leur répartition spatiale. Nous avons donc adapté cette technique à la microscopie champ proche, la pointe AFM conductrice faisant office de grille. Sur des transistors dépourvus de grille spécialement préparés pour l’occasion, nous avons pu montrer la faisabilité de la technique, en accord satisfaisant avec les mesures macroscopiques. Nous mesurons un signal que nous associons à un courant pompé. Cependant, le signal est déformé comparativement aux mesures macroscopiques. Un modèle physique reste à développer puisque dans notre cas, les charges minoritaires doivent traverser depuis la source et le drain un espace non polarisé par la grille. Par la suite, un dispositif de cartographie des défauts d'interface, éventuellement résolue en énergie, pourra être développé. / The rapid progress of the microelectronic is obtained by the strong reduction of the dimensions of the MOS transistor. In order to reduce the leakage currents SiO2 is nox replaced by HfO2, but new dielectrics with a high permittivity (high-k) will have to be integrated in the future so that the progession continues. The atomic force microscope (AFM) in Conductive-AFM (C-AFM) mode is an ideal tools for the electrical characterization of thin oxide films at the nanometric scale. In our work, we have tried to study the limits of the C-AFM. C-AFM consists in using an AFM tip as a top electrode in order to perform Intensity-Current (I-V) curves or mapping the current. We have tried and identify the phenomenon which lead to the degradation of the dielectric layer during the application of the positive voltage bias on the tip, which results in a deformation of the surface under study. We have shown that it is a thermal effect due to a large density of current, which is different from dielectric induced breakdown epitaxy (DBIE) observed on the devices, and which may even lead to the degradation of the susbstrate at the interface. This phenomon is favored by the presence of water on the surface although it is not its consequence. This confirms that such electrical measurements should be performed in ultra-high vacuum in spite of the consequences in terms of complexity of the measurement setup. As a consequence, the study of the dielectric material are questionned since the degradation process is partly due to the AFM technique itself and does not allow to extrapolate easily the behaviour of the integrated device. Moreover, the statistical study of the degradation of the layer (Weibull), commonly used, is affected by a bias (measurements are interdependent). In the same way, the modeling of the conduction through the layer must be questionned because the surface of the electrical contact between the tip and the dielectric layer remains a very variable parameter. The charge pumping technique, which consists in caracterizing the traps at the semiconductor / dielectric interface by filling/emptying them with the application of an alternating gate voltage. It allows to extract the states density (Dit(E) and the capture cross section (σ(E)) but does not provide any information about their repartition on the interface. So, we have adapted this technique to the scanning probe microscopy with the conducting AFM probe as a gate. Using gate-less transistors fabricated in the frame of this work, we have demonstrated the feasability of this technique with a satisfying agreement with macroscopic measurements. We are able to measure a signal that can be related to charge pumping. However, the signal is distorted compared to macroscopic measurements. Modeling is needed because in our case, minority carriers must travel from source to drain via a non polarised area. As a perspective, an energetically resolved method to map the interfacial defects might be developed.

I have worked on many projects, but there are several things that they all had in common. First, nearly all projects involved searching for the structural parameters that governed the macroscopic properties of the polymers and composite materials. A second common denominator is that even though my work was performed in an “academic context”, the goals were targeted toward industrial needs. Lastly, the methods and procedures were similar; they were all based on experimental results obtained for various scales of measurement (see Fig. 1). Hence, multi-scale modeling was very useful and beneficial for these projects. The models developed (mainly numerical and sometimes analytical) were initially derived from experimental evidence and then validated and improved with further experimentation. The refined models provided an efficient means of: (i) optimizing the composites according to specific needs, (ii) better understanding the hierarchical relations between the different scales, (iii) controlling the micro or meso structure and thereby the macroscopic properties. This study of the relations between structure and properties was performed on a wide variety of physical properties and materials. However, the electric and dielectric properties of composites constituted the major- ity of it and will be presented in this report. The remaining property investigations provided supplemental but valuable information. This work often requires altering various conventional experimental techniques or using well-known techniques for new purposes. I also developed, when needed, several unconventional but necessary measurement techniques. This report contains two major parts which are separated according to the nature of the fillers: Part I : Conducting fillers. In the first part, the main interest both for application and fundamental point of view, is related to the changes in properties in the vicinity of the sharp percolation transition. After a brief introduction to the percolation theory, this part will be subdivided in three chapters: Chapter 1. presents a numerical method that correlates the mesostructure to the macroscopic electrical properties both in two and three dimensions. Chapter 2. will show that an external variable (the mechanical stress) may largely alter the microstruc- ture of the percolating network within composites as revealed the macroscopic conductivity. The understanding of the mesoscale changes will be based on the chemical structure of the polymer matrix. Chapter 3. is devoted to the description of a unique case in term of percolation behavior, which made possible the control of the phase arrangement within the composite and thereby the control of the macroscopic resistivity. p. 2 Multiscale relationships in polymer–based heterogeneous systems. . . Part II : Insulating fillers. In the second part, the main interest is to obtain good electrical insulators, i.e. that can withstand large electric fields. This part thus starts with a brief introduction to the common failure mechanisms, associated with the dielectric breakdown and is also divided in three chapters: Chapter 4. is devoted to the description of a numerical simulation of the relationships between mesostructure and dielectric breakdown. Chapter 5. reveals the influence of the processing conditions of a composite utilized in the industry on the microstructure and the quantitative consequences on breakdown properties. Chapter 6. presents the aging of these composites under “real word” conditions which will further be compared to accelerated aging performed in controlled conditions, in the laboratory. A comparison of the two aging situations will furnish a quantitative understanding of the relative influence of the chemical and physical contributions to the aging process. This report will then be concluded with a description of the current and future projects.

The impact of physical design characteristics on backend dielectric reliability was modeled. The impact of different interconnect geometries on backend low-k time dependent dielectric breakdown was reported and modeled. Physical design parameters that are crucial to backend dielectric reliability were identified. A methodology was proposed for determining chip reliability but combining the insights gathered by modeling the impact of physical design on backend dielectric breakdown. A methodology to model variation in device parameters and characteristics was proposed. New methods of electrical and physical parameter extraction were proposed. Models that consider systematic and random source of variation in electrical and physical parameters of CMOS devices were proposed, to aid in circuit design and timing analysis.

Frontend and backend wearout mechanisms are major reliability concerns for modern microprocessors. In this research, a framework which contains modules for negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), hot carrier injection (HCI), gate-oxide breakdown (GOBD), backend time-dependent dielectric breakdown (BTDDB), electromigration (EM), and stress-induced voiding (SIV) is proposed to analyze the impact of each wearout mechanism on state-of-art microprocessors and to accurately estimate microprocessor lifetimes due to each wearout mechanism. Taking into account the detailed thermal profiles, electrical stress profiles and a variety of use scenarios, composed of a fraction of time in operation, a fraction of time in standby, and a fraction of time when the system is off, this work provides insight into lifetime-limiting wearout mechanisms, along with the reliability-critical microprocessor functional units for a system. This enables circuit designers to know if their designs will achieve an adequate lifetime and further make any updates in the designs to enhance reliability prior to committing the designs to manufacture.

L'objectif de cette thèse est d'étudier la fiabilité et la cyclabilité des jonctions Tunnel magnétique pour mieux comprendre les mécanismes de dégradation et de claquage de la barrière. Une étude de l'endurance de la barrière MgO jusqu'au claquage électrique est présentée. Les échantillons ont été testés sous un mode impulsionnel. Par l'étude de l'effet de retard entre des impulsions successives, une durée de vie optimale des JTM est observée pour une valeur intermédiaire de retard entre les impulsions correspondant à un compromis optimal entre la densité moyenne de charge piégée dans la barrière et la modulation temporelle de charge. En outre, un modèle de piégeage / dépiégeage de charge a été développé qui appuie cette interprétation. L'étude souligne le rôle des pièges de charges dans le mécanisme de claquage de la barrière tunnel. Elle montre aussi que l'endurance extrêmement longue pourrait être obtenue en réduisant la densité des sites de piégeage d'électrons dans la barrière tunnel. Puis, une étude de l'endurance et le bruit basse fréquence a été dans les jonctionS CoFeB/MgO/CoFeB pour STT-MRAM ou TA-MRAM. Une corrélation a été observée et expliquée par la présence de sites de piégeage d'électrons dans la barrière de MgO et le rôle des phénomènes de charge/ décharge à la fois dans la fiabilité et la puissance du bruit en 1 / f électrique. Ces résultats prouvent que le test du bruit basse fréquence peut être utilisé comme une caractérisation prédictive de l'endurance. Enfin, en perspectives, des mesures complémentaires en été proposées pour développer plus le modèle de charge/décharge, une optimisation de la barrière pourrait ainsi être réaliser pour réduire le nombre des pièges de charge au sein de la barrière et par conséquent améliorer la fiabilité des jonctions Tunnel. / The thesis objective is to study the Magnetic Tunnel Junction reliability and cyclability to more understand the barrier breakdown mechanisms. An investigation of barrier endurance till electrical breakdown in MgO-based magnetic tunnel junctions (MTJs) is presented. Samples were tested under pulsed electrical stress. By studying the effect of delay between successive pulses, an optimum endurance of MTJs is observed for an intermediate value of delay between pulses corresponding to an optimum trade-off between the average density of charge trapped in the barrier and the amplitude of its time-modulation at each voltage pulse. Furthermore, a charge trapping/detrapping model was developed which support this interpretation. The study emphasizes the role of electron trapping/detrapping mechanisms on the tunnel barrier reliability. It also shows that extremely long endurance could be obtained in MTJs by reducing the density of electron trapping sites in the tunnel barrier. Then the write endurance and the 1/f noise of electrical origin were characterized in CoFeB/MgO/CoFeB MTJ for STT-MRAM or TA-MRAM. A correlation was observed and explained by the presence of electron trapping sites in the MgO barrier and the role of electron trapping/detrapping phenomena in both the MTJ reliability and its 1/f electrical noise power. These results suggest that 1/f noise could be used as a predictive characterization of the MTJ endurance. Finally, as thesis perspectives, some complement measurements were proposed to further investigate this model and an optimization of MgO barrier which could be carried out to reduce the density of these trapping sites was presented to ameliorate the MTJs reliability.

No description available.

科学研究費補助金 研究種目:基盤研究(A)(2) 課題番号:13305005 研究代表者:近藤 博基 研究期間:2001-2004年度