Global ETD Search

1	Modeling reliability in copper/low-k interconnects and variability in cmos Bashir, Muhammad Muqarrab 20 May 2011 (has links) The impact of physical design characteristics on backend dielectric reliability was modeled. The impact of different interconnect geometries on backend low-k time dependent dielectric breakdown was reported and modeled. Physical design parameters that are crucial to backend dielectric reliability were identified. A methodology was proposed for determining chip reliability but combining the insights gathered by modeling the impact of physical design on backend dielectric breakdown. A methodology to model variation in device parameters and characteristics was proposed. New methods of electrical and physical parameter extraction were proposed. Models that consider systematic and random source of variation in electrical and physical parameters of CMOS devices were proposed, to aid in circuit design and timing analysis. Weibull Copper interconnects Low-k TDDB Dielectric breakdown Interconnect reliability Low-k dielectrics CMOS variation Systematic variation Random variation With-die variation System reliability Chip reliability Weibull distribution Breakdown (Electricity) Integrated circuits