Huang, Lin. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 218-232). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Preface --- p.1 / Chapter 1.2 --- Background --- p.5 / Chapter 1.3 --- Contributions --- p.6 / Chapter 1.3.1 --- Lifetime Reliability Modeling --- p.6 / Chapter 1.3.2 --- Simulation Framework --- p.7 / Chapter 1.3.3 --- Applications --- p.9 / Chapter 1.4 --- Thesis Outline --- p.10 / Chapter I --- Modeling --- p.12 / Chapter 2 --- Lifetime Reliability Modeling --- p.13 / Chapter 2.1 --- Notation --- p.13 / Chapter 2.2 --- Assumption --- p.16 / Chapter 2.3 --- Introduction --- p.16 / Chapter 2.4 --- Related Work --- p.19 / Chapter 2.5 --- System Model --- p.21 / Chapter 2.5.1 --- Reliability of A Surviving Component --- p.22 / Chapter 2.5.2 --- Reliability of a Hybrid k-out-of-n:G System --- p.26 / Chapter 2.6 --- Special Cases --- p.31 / Chapter 2.6.1 --- Case I: Gracefully Degrading System --- p.31 / Chapter 2.6.2 --- Case II: Standby Redundant System --- p.33 / Chapter 2.6.3 --- Case III: l-out-of-3:G System with --- p.34 / Chapter 2.7 --- Numerical Results --- p.37 / Chapter 2.7.1 --- Experimental Setup --- p.37 / Chapter 2.7.2 --- Experimental Results and Discussion --- p.40 / Chapter 2.8 --- Conclusion --- p.43 / Chapter 2.9 --- Appendix --- p.44 / Chapter II --- Simulation Framework --- p.47 / Chapter 3 --- AgeSim: A Simulation Framework --- p.48 / Chapter 3.1 --- Introduction --- p.48 / Chapter 3.2 --- Preliminaries and Motivation --- p.51 / Chapter 3.2.1 --- Prior Work on Lifetime Reliability Analysis of Processor- Based Systems --- p.51 / Chapter 3.2.2 --- Motivation of This Work --- p.53 / Chapter 3.3 --- The Proposed Framework --- p.54 / Chapter 3.4 --- Aging Rate Calculation --- p.57 / Chapter 3.4.1 --- Lifetime Reliability Calculation --- p.58 / Chapter 3.4.2 --- Aging Rate Extraction --- p.60 / Chapter 3.4.3 --- Discussion on Representative Workload --- p.63 / Chapter 3.4.4 --- Numerical Validation --- p.65 / Chapter 3.4.5 --- Miscellaneous --- p.66 / Chapter 3.5 --- Lifetime Reliability Model for MPSoCs with Redundancy --- p.68 / Chapter 3.6 --- Case Studies --- p.70 / Chapter 3.6.1 --- Dynamic Voltage and Frequency Scaling --- p.71 / Chapter 3.6.2 --- Burst Task Arrival --- p.75 / Chapter 3.6.3 --- Task Allocation on Multi-Core Processors --- p.77 / Chapter 3.6.4 --- Timeout Policy on Multi-Core Processors with Gracefully Degrading Redundancy --- p.78 / Chapter 3.7 --- Conclusion --- p.79 / Chapter 4 --- Evaluating Redundancy Schemes --- p.83 / Chapter 4.1 --- Introduction --- p.83 / Chapter 4.2 --- Preliminaries and Motivation --- p.85 / Chapter 4.2.1 --- Failure Mechanisms --- p.85 / Chapter 4.2.2 --- Related Work and Motivation --- p.86 / Chapter 4.3 --- Proposed Analytical Model for the Lifetime Reliability of Proces- sor Cores --- p.88 / Chapter 4.3.1 --- "Impact of Temperature, Voltage, and Frequency" --- p.88 / Chapter 4.3.2 --- Impact of Workloads --- p.92 / Chapter 4.4 --- Lifetime Reliability Analysis for Multi-core Processors with Vari- ous Redundancy Schemes --- p.95 / Chapter 4.4.1 --- Gracefully Degrading System (GDS) --- p.95 / Chapter 4.4.2 --- Processor Rotation System (PRS) --- p.97 / Chapter 4.4.3 --- Standby Redundant System (SRS) --- p.98 / Chapter 4.4.4 --- Extension to Heterogeneous System --- p.99 / Chapter 4.5 --- Experimental Methodology --- p.101 / Chapter 4.5.1 --- Workload Description --- p.102 / Chapter 4.5.2 --- Temperature Distribution Extraction --- p.102 / Chapter 4.5.3 --- Reliability Factors --- p.103 / Chapter 4.6 --- Results and Discussions --- p.103 / Chapter 4.6.1 --- Wear-out Rate Computation --- p.103 / Chapter 4.6.2 --- Comparison on Lifetime Reliability --- p.105 / Chapter 4.6.3 --- Comparison on Performance --- p.110 / Chapter 4.6.4 --- Comparison on Expected Computation Amount --- p.112 / Chapter 4.7 --- Conclusion --- p.118 / Chapter III --- Applications --- p.119 / Chapter 5 --- Task Allocation and Scheduling for MPSoCs --- p.120 / Chapter 5.1 --- Introduction --- p.120 / Chapter 5.2 --- Prior Work and Motivation --- p.122 / Chapter 5.2.1 --- IC Lifetime Reliability --- p.122 / Chapter 5.2.2 --- Task Allocation and Scheduling for MPSoC Designs --- p.124 / Chapter 5.3 --- Proposed Task Allocation and Scheduling Strategy --- p.126 / Chapter 5.3.1 --- Problem Definition --- p.126 / Chapter 5.3.2 --- Solution Representation --- p.128 / Chapter 5.3.3 --- Cost Function --- p.129 / Chapter 5.3.4 --- Simulated Annealing Process --- p.130 / Chapter 5.4 --- Lifetime Reliability Computation for MPSoC Embedded Systems --- p.133 / Chapter 5.5 --- Efficient MPSoC Lifetime Approximation --- p.138 / Chapter 5.5.1 --- Speedup Technique I - Multiple Periods --- p.139 / Chapter 5.5.2 --- Speedup Technique II - Steady Temperature --- p.139 / Chapter 5.5.3 --- Speedup Technique III - Temperature Pre- calculation --- p.140 / Chapter 5.5.4 --- Speedup Technique IV - Time Slot Quantity Control --- p.144 / Chapter 5.6 --- Experimental Results --- p.144 / Chapter 5.6.1 --- Experimental Setup --- p.144 / Chapter 5.6.2 --- Results and Discussion --- p.146 / Chapter 5.7 --- Conclusion and Future Work --- p.152 / Chapter 6 --- Energy-Efficient Task Allocation and Scheduling --- p.154 / Chapter 6.1 --- Introduction --- p.154 / Chapter 6.2 --- Preliminaries and Problem Formulation --- p.157 / Chapter 6.2.1 --- Related Work --- p.157 / Chapter 6.2.2 --- Problem Formulation --- p.159 / Chapter 6.3 --- Analytical Models --- p.160 / Chapter 6.3.1 --- Performance and Energy Models for DVS-Enabled Pro- cessors --- p.160 / Chapter 6.3.2 --- Lifetime Reliability Model --- p.163 / Chapter 6.4 --- Proposed Algorithm for Single-Mode Embedded Systems --- p.165 / Chapter 6.4.1 --- Task Allocation and Scheduling --- p.165 / Chapter 6.4.2 --- Voltage Assignment for DVS-Enabled Processors --- p.168 / Chapter 6.5 --- Proposed Algorithm for Multi-Mode Embedded Systems --- p.169 / Chapter 6.5.1 --- Feasible Solution Set --- p.169 / Chapter 6.5.2 --- Searching Procedure for a Single Mode --- p.171 / Chapter 6.5.3 --- Feasible Solution Set Identification --- p.171 / Chapter 6.5.4 --- Multi-Mode Combination --- p.177 / Chapter 6.6 --- Experimental Results --- p.178 / Chapter 6.6.1 --- Experimental Setup --- p.178 / Chapter 6.6.2 --- Case Study --- p.180 / Chapter 6.6.3 --- Sensitivity Analysis --- p.181 / Chapter 6.6.4 --- Extensive Results --- p.183 / Chapter 6.7 --- Conclusion --- p.185 / Chapter 7 --- Customer-Aware Task Allocation and Scheduling --- p.186 / Chapter 7.1 --- Introduction --- p.186 / Chapter 7.2 --- Prior Work and Problem Formulation --- p.188 / Chapter 7.2.1 --- Related Work and Motivation --- p.188 / Chapter 7.2.2 --- Problem Formulation --- p.191 / Chapter 7.3 --- Proposed Design-Stage Task Allocation and Scheduling --- p.192 / Chapter 7.3.1 --- Solution Representation and Moves --- p.193 / Chapter 7.3.2 --- Cost Function --- p.196 / Chapter 7.3.3 --- Impact of DVFS --- p.198 / Chapter 7.4 --- Proposed Algorithm for Online Adjustment --- p.200 / Chapter 7.4.1 --- Reliability Requirement for Online Adjustment --- p.201 / Chapter 7.4.2 --- Analytical Model --- p.203 / Chapter 7.4.3 --- Overall Flow --- p.204 / Chapter 7.5 --- Experimental Results --- p.205 / Chapter 7.5.1 --- Experimental Setup --- p.205 / Chapter 7.5.2 --- Results and Discussion --- p.207 / Chapter 7.6 --- Conclusion --- p.211 / Chapter 7.7 --- Appendix --- p.211 / Chapter 8 --- Conclusion and Future Work --- p.214 / Chapter 8.1 --- Conclusion --- p.214 / Chapter 8.2 --- Future Work --- p.215 / Bibliography --- p.232

The impact of physical design characteristics on backend dielectric reliability was modeled. The impact of different interconnect geometries on backend low-k time dependent dielectric breakdown was reported and modeled. Physical design parameters that are crucial to backend dielectric reliability were identified. A methodology was proposed for determining chip reliability but combining the insights gathered by modeling the impact of physical design on backend dielectric breakdown. A methodology to model variation in device parameters and characteristics was proposed. New methods of electrical and physical parameter extraction were proposed. Models that consider systematic and random source of variation in electrical and physical parameters of CMOS devices were proposed, to aid in circuit design and timing analysis.

With continued feature size reduction in microelectronics and with more than a billion transistors on a single integrated circuit (IC), on-chip interconnection has become a challenge in terms of processing-, electrical-, thermal-, and mechanical perspective. Today’s high-performance ICs have on-chip back-end-of-line (BEOL) layers that consist of copper traces and vias interspersed with low-k dielectric materials. These layers have thicknesses in the range of 100 nm near the transistors and 1000 nm away from the transistors close to the solder bumps. In such BEOL layered stacks, cracking and/or delamination is a common failure mode due to the low mechanical and adhesive strength of the dielectric materials as well as due to high thermally-induced stresses. However, there are no available cohesive zone models and parameters to study such interfacial cracks in sub-micron thick microelectronic layers. This work focuses on developing framework based on cohesive zone modeling approach to study interfacial delamination in sub-micron thick layers. Such a framework is then successfully applied to predict microelectronic device reliability. As intentionally creating pre-fabricated cracks in such interfaces is difficult, this work examines a combination of four-point bend and double-cantilever beam tests to create initial cracks and to develop cohesive zone parameters over a range of mode-mixity. Similarly, a combination of four-point bend and end-notch flexure tests is used to cover additional range of mode-mixity. In these tests, silicon wafers obtained from wafer foundry are used for experimental characterization. The developed parameters are then used in actual microelectronic device to predict the onset and propagation of crack, and the results from such predictions are successfully validated with experimental data. In addition, nanoindenter-based shear test technique designed specifically for this study is demonstrated. The new test technique can address different mode mixities compared to the other interfacial fracture characterization tests, is sensitive to capture the change in fracture parameter due to changes in local trace pattern variations around the vicinity of bump and the test mimics the forces experienced by the bump during flip-chip assembly reflow process. Through this experimental and theoretical modeling research, guidelines are also developed for the reliable design of BEOL stacks for current and next-generation microelectronic devices.