Dramatic advances are taking place in the microelectronic industry. The feature size continues to scale down and it is expected that the minimum feature size on the integrated circuit is expected to reach 9 nm by 2016, and there will be more than 8 billion transistors on a 310 cm² chip, according to various available roadmaps. Subsequently, this reduction in feature size would require the first-level input-output interconnects to decrease in pitch size to meet the increased number of transistors on the chip. Also, to minimize the on-chip interconnect delay, development of low-K dielectric/copper will become increasingly common in future devices. However, due to the low fracture strength of low-K dielectric, it is essential that the first-level interconnects exert minimal force on the die pads and therefore, do not crack or delaminate the low-K dielectric material. It is also preferable to have a wafer-level packaging approach to facilitate test-and-burn in and to produce known-good dies. Based on these growing demands from the microelectronics industry, there is a compelling need to develop innovative interconnect technologies. This thesis aims to develop one such innovative interconnect — G-Helix interconnect. G-Helix is a scalable lithography-based wafer-level electroplated compliant interconnect that has the potential to meet the fine-pitch first-level chip-to-substrate interconnect requirements. The three-mask fabrication of G-Helix is based on lithography, electroplating and molding (LIGA-like) technologies, and this fabrication can be easily integrated into large-area wafer-level fine-pitch batch processing. In this work, the fabrication, assembly, experimental reliability testing, and numerical physics-based modeling of the G-Helix interconnects will be presented. The fabrication of the interconnects will be demonstrated at 100μm pitch on a 20 x 20 mm die in a class 10/1000 cleanroom facility. The wafers with compliant interconnects will be singulated into individual dies and assembled on substrates using Pb/Sn eutectic solder. The assembly will then be subjected to air-to-air thermal cycling between 0℃and 100℃ and the reliability of the compliant interconnect will be assessed. In addition to the thermo-mechanical reliability testing, some of the dies with free-standing interconnects will also be used for measuring the compliance of the interconnects by compressing with a nanoindenter. In parallel to the experimental research, a numerical analysis study will also be carried out. The numerical model will use direction-, temperature, time-dependent, and time independent material constitutive properties as appropriate. The thermo-mechanical fatigue life of the compliant interconnect assembly will be determined and compared with the experimental data. Recommendations will be developed for further enhancement of reliability and reduction in pitch size.

This study mainly evaluated the thermo-mechanical reliability of lead-free packaging techniques for attaching large-area chip. With 3 MPa pressure, a low-temperature (<300oC) sintering technique enabled by a nano-scale silver paste was developed for attaching 100 mm2 silicon die. This new lead-free packaging technique for die-attachment was compared with soldering by vacuum reflow. Lead-free solder SAC305 and SN100C were selected and used in this work since they were widely used in electronic packaging industry. Inspection of as-prepared die-attachments by X-ray and optical microscopy (observation of cross-section) showed that the voids percentage in solder joint was less than 5% and no voids was observed at the scale of hundreds of micron in sintered silver joint. Then these die-attachment were thermal cycled with the temperature range from -40oC to 125oC. Deduction of curvature and residual stresses were found for both soldered and sintered die-attachment. After 800 cycles, the residual stresses in silicon-solder-copper sample already decreased to around 0. The SEM images of solder and silver joint after 800 thermal cycles showed that cracks longer than 2.5 mm already grew in both kinds of solder joint (die-attachment of Si-Solder-Copper). In contrast, no cracks or voids at the scale of hundreds of micron were defected in silver joint. Based on these observation, different mode of stress-relaxation were proposed for sintered silver and solder, respectively. While solder joint released stresses by crack growth, the silver joint relied on the deformation of porous structure, and plastic deformation may occur. The pressure-sintering process with double printing and drying was proved to be a reliable process to produce sintered - silver bonding with high strength. The reliability of silver joint was better than that of SAC305 or SN100C. Besides, the technique of measuring the curvature by laser scanning, introduced in this work, showed its significance by directly reflecting the bonding integrity of die-attachment. As a nondestructive testing technique, It was a cheaper and faster way to examine the die-attachment. Additionally, it overcame the disadvantage of X-ray Inspection: it was of the ability to differentiate between layers of die-attachment. / Master of Science

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The main objective of this dissertation is to explore and develop computer-aided-design methodologies and optimization techniques for reliability, performance, and power of through-silicon-via-based 3D IC designs. Through-silicon-via (TSV), a vertical interconnect element between dies, is the key enabling technology in 3D ICs. This new design element provides unprecedented design freedom as well as challenges. To maximize benefits and overcome challenges in TSV-based 3D ICs, new analysis methodologies and optimization techniques should be developed. In this dissertation, first, the robustness of 3D power delivery network is assessed under different power/ground TSV placement schemes and TSV RC variations. Next, thermo-mechanical stress and reliability problems are examined in full-chip/stack scale using the principle of linear superposition of stress tensors. Finally, physical design methods for low power 3D designs are explored to enhance the 3D power benefit over the 2D counterpart.

With continued feature size reduction in microelectronics and with more than a billion transistors on a single integrated circuit (IC), on-chip interconnection has become a challenge in terms of processing-, electrical-, thermal-, and mechanical perspective. Today’s high-performance ICs have on-chip back-end-of-line (BEOL) layers that consist of copper traces and vias interspersed with low-k dielectric materials. These layers have thicknesses in the range of 100 nm near the transistors and 1000 nm away from the transistors close to the solder bumps. In such BEOL layered stacks, cracking and/or delamination is a common failure mode due to the low mechanical and adhesive strength of the dielectric materials as well as due to high thermally-induced stresses. However, there are no available cohesive zone models and parameters to study such interfacial cracks in sub-micron thick microelectronic layers. This work focuses on developing framework based on cohesive zone modeling approach to study interfacial delamination in sub-micron thick layers. Such a framework is then successfully applied to predict microelectronic device reliability. As intentionally creating pre-fabricated cracks in such interfaces is difficult, this work examines a combination of four-point bend and double-cantilever beam tests to create initial cracks and to develop cohesive zone parameters over a range of mode-mixity. Similarly, a combination of four-point bend and end-notch flexure tests is used to cover additional range of mode-mixity. In these tests, silicon wafers obtained from wafer foundry are used for experimental characterization. The developed parameters are then used in actual microelectronic device to predict the onset and propagation of crack, and the results from such predictions are successfully validated with experimental data. In addition, nanoindenter-based shear test technique designed specifically for this study is demonstrated. The new test technique can address different mode mixities compared to the other interfacial fracture characterization tests, is sensitive to capture the change in fracture parameter due to changes in local trace pattern variations around the vicinity of bump and the test mimics the forces experienced by the bump during flip-chip assembly reflow process. Through this experimental and theoretical modeling research, guidelines are also developed for the reliable design of BEOL stacks for current and next-generation microelectronic devices.