Wireless visual sensor network is an emerging field which has proveduseful in many applications, including industrial control and monitoring,surveillance, environmental monitoring, personal care and the virtual world.Traditional imaging systems used a wired link, centralized network, highprocessing capabilities, unlimited storage and power source. In manyapplications, the wired solution results in high installation and maintenancecosts. However, a wireless solution is the preferred choice as it offers lessmaintenance, infrastructure costs and greater scalability.The technological developments in image sensors, wirelesscommunication and processing platforms have paved the way for smartcamera networks usually referred to as Wireless Visual Sensor Networks(WVSNs). WVSNs consist of a number of Visual Sensor Nodes (VSNs)deployed over a large geographical area. The smart cameras can performcomplex vision tasks using limited resources such as batteries or alternativeenergy sources, embedded platforms, a wireless link and a small memory.Current research in WVSNs is focused on reducing the energyconsumption of the node so as to maximise the life of the VSN. To meet thischallenge, different software and hardware solutions are presented in theliterature for the implementation of VSNs.The focus in this thesis is on the exploration of energy efficientreconfigurable architectures for VSNs by partitioning vision tasks on software,hardware platforms and locality. For any application, some of the vision taskscan be performed on the sensor node after which data is sent over the wirelesslink to the server where the remaining vision tasks are performed. Similarly,at the VSN, vision tasks can be partitioned on software and the hardwareplatforms.In the thesis, all possible strategies are explored, by partitioning visiontasks on the sensor node and on the server. The energy consumption of thesensor node is evaluated for different strategies on software platform. It isobserved that performing some of the vision tasks on the sensor node andsending compressed images to the server where the remaining vision tasks areperformed, will have lower energy consumption.In order to achieve better performance and low power consumption,Field Programmable Gate Arrays (FPGAs) are introduced for theimplementation of the sensor node. The strategies with reasonable designtimes and costs are implemented on hardware-software platform. Based onthe implementation of the VSN on the FPGA together with micro-controller,the lifetime of the VSN is predicted using the measured energy values of theplatforms for different processing strategies. The implementation resultsprove our analysis that a VSN with such characteristics will result in a longerlife time.

The wireless visual sensor network is an emerging field which is formed by deploying many visual sensor nodes in the field and in which each individual visual sensor node contains an image sensor, on board processor, memory and wireless transceiver. In comparison to the traditional wireless sensor networks, which operate on one dimensional data, the wireless visual sensor networks operate on two dimensional data which requires higher processing power and communication bandwidth. Research focus within the field of wireless visual sensor networks has been on two different extremes, involving either sending raw data to the central base station without local processing or conducting all processing locally at the visual sensor node and transmitting only the final results.This research work focuses on determining an optimal point of hardware/software partitioning at the visual sensor node as well as partitioning tasks between local and central processing, based on the minimum energy consumption for the vision processing tasks. Different possibilities in relation to partitioning the vision processing tasks between hardware, software and locality for the implementation of the visual sensor node, used in wireless visual sensor networks have been explored. The effect of packets relaying and node density on the energy consumption and implementation of the individual wireless visual sensor node, when used in a multi-hop wireless visual sensor networks have also been explored.The lifetime of the visual sensor node is predicted by evaluating the energy requirement of the embedded platform with a combination of the Field Programmable Gate Arrays (FPGA) and the micro-controller for the implementation of the visual sensor node and, in addition, taking into account the amount of energy required for receiving/forwarding the packets of other nodes in the multi-hop network.Advancements in FPGAs have been the motivation behind their choice as the vision processing platform for implementing visual sensor node. This choice is based on the reduced time-to-market, low Non-Recurring Engineering (NRE) cost and programmability as compared to ASICs. The other part of the architecture of the visual sensor node is the SENTIO32 platform, which is used for vision processing in the software implementation of the visual sensor node and for communicating the results to the central base station in the hardware implementation (using the RF transceiver embedded in SENTIO32).

<p>This report is a master degree thesis in electronics that examines if weak relations can be used in TracFeed. TracFeed is a simulation tool designed to aid in the dimensioning of the power supply</p><p>system for electrical railroads. The program was originally developed by Adtranz and is today further enhanced by Balfour Beatty Rail AB.</p><p>When using weak relations there will be fewer truncations of the steps and therefore the response time will decrease. The purpose of this thesis is to study how much time that can be gained in</p><p>different types of simulations and in which way the result is effected because of weak relations. The theoretical part explains the fundamentals concerning electrical trains and how trains are</p><p>modelled in TracFeed. The calculation kernel used by TracFeed is called SIMPOW and it is described as well as the modelling language which is used to create the train models.</p><p>Weak relations are tested in two simulations. The result from those simulations shows that if a displacement in simulated time of the output is acceptable and there are many trains active</p><p>simultaneously weak relations are an interesting alternative.</p>

<p>Eskilstuna Elektronikpartner (EEPAB) är ett elektronikföretag som tillverkar vinkelgivare till bland annat kranar som är monterade på lastbilsflak.</p><p>För att EEPAB på ett intressant sätt ska kunna demonstrera sin produkt på mässor har en demonstrator tagits fram. Denna demonstrator består av en fjärrstyrd grävmaskin och en elektronikenhet, som hanterar den analoga signalen från vinkelgivaren. Resultatet, som är vinkelgivarens lutning i grader, presenteras på två sjusegmentdisplayer som är placerade på grävmaskinens bägge sidor. Vinkeln skickas även trådlöst från elektronikenheten, via Bluetooth, till en PC. Grävmaskinens batteri (7,2V) strömförsörjer all hårdvara, vilket gör att demonstratorn är helt portabel.</p><p>Denna rapport beskriver block för block de olika programfunktioner samt hårdvara, som behövs till en färdig och fungerande demonstrator.</p> / <p>Eskilstuna Elektronikpartner (EEPAB) is an electronics company located in Eskilstuna that produces angle sensors to, for instance, cranes mounted on truck beds.</p><p>For EEPAB to be able to demonstrate their product on fairs in an interesting way, a demonstrator has been made. The demonstrator consists of a remote controlled excavator and an electronic unit which handles the analog signal from the sensor. The result, which is the angle of the sensor in degrees, is presented on two sevensegment displays that are placed on both sides of the excavator. The angle is also sent wirelessly from the electronic unit via Bluetooth to a PC. The battery of the excavator powers all of the hardware, making the demonstrator fully portable.</p><p>This thesis report describes the various programfunctions and hardware, part by part, necessary for a complete and functioning demonstrator.</p>

<p>En RMRC, Rail Mounted Railway Crane, är en kran för hantering av containertrafik till och från järnvägsvagnar. Kranen som är helt manuellt styrd utrustas med en semiautomatik som hjälper operatören att positionera kranen. Målpositionen för containern kommer från terminalens logistiksystem. För positioneringen har en lämplig regulator tagits fram som tar hänsyn till den mekaniska påverkan på motorer och växellådor som finns vid acceleration och retardation. Regulatorn har tagits fram och testats i en simuleringsmiljö. Den har sedan implementerats i ett PLC-system och provkörts i labmiljö med PLC och motorer. Regulatorn har förbättrad prestanda jämfört med den regulator som tidigare använts för andra typer av kranar. Den är också lättare att trimma in vid idriftsättning.För positionsåterföringen på de tre rörelserna lyft, tralla och kranåk, har olika typer av givare undersökts och rekommenderat.</p>

<p>The work presented in this paper is about the development of a collision avoidance systemfor a mobile telepresence robot developed by the company Gira technologies AB.The robot is designed to extend the length of time elderly can stay in their homes beforerequiring full-time staed care. The collision avoidance system is needed to help the userto avoid running in to objects or down a stairway. The design must be capable of beingimplemented at low cost, and should not look overtly "robotic" as this would not resultin an appealing industrial design.</p><p>Herein, dierent techniques are presented and analyzed to nd the best suitable solutionfor the robot. In particular a lot of work is done in taking measurements to nd theright characteristics for the sensors according dierent mounting angles, dierent objectsand distances. A solution is chosen and calculations are made to nd the best positionsto place the sensors to get the best results.</p><p>A complete solution is presented and implemented in the current system and testedto work as expected.</p>

<p>The task for this thesis was to develop, construct and evaluate a multi‐bus communication system,connected to a PC via USB and capable of communicating in CAN, I2C and SPI and develop drivers for itin National Instruments LabVIEW.In the beginning a study was made of the communication buses followed by an investigation of whattype of hardware that could accomplish this task. A microcontroller unit was selected andprogrammed in MikroElektronika MikroC Pro v.3.2 to act as the interface between the communicationbusses and PC. A PCB prototype of the system was constructed by using Eagle Cad software v.5.6.0. General drivers for this system where created in LabVIEW v.8.6.1 so the end‐user simply can createtheir own applications and control the compatible hardware depending on their type of purposes. Thesystem was tested on criteria’s such as: speed, power consumption, burst performance andtransmission length depending on which communication bus was used.</p>

<p>In this thesis, both a method and a tool to enable efficient memory synthesis for real-time video processing systems on field programmable logic array are presented. In real-time video processing system (RTVPS), a set of operations are repetitively performed on every image frame in a video stream. These operations are usually computationally intensive and, depending on the video resolution, can also be very data transfer dominated. These operations, which often require data from several consecutive frames and many rows of data within each frame, must be performed accurately and under real-time constraints as the results greatly affect the accuracy of application. Application domains of these systems include object recognition, object tracking and surveillance.</p><p>Developments in field programmable gate array (FPGA) have been the motivation for choosing them as the platform for implementing RTVPS. Essential logic resources required in RTVPS operation are currently available optimized and embedded in modern FPGAs. One such resource is the embedded memory used for data buffering during real-time video processing. Each data buffer corresponds to a row of pixels in a video frame, which is allocated using a synthesis tool that performs the mapping of buffers to embedded memories. This approach has been investigated and proven to be inefficient. An efficient alternative employing resource sharing and allocation width pipelining will be discussed in this thesis.</p><p>A method for the optimal use of these embedded memories and, additionally, a tool supporting automatic generation of hardware descriptions language (HDL) codes for the synthesis of the memories according to the developed method are the main focus of this thesis. This method consists of the memory architecture, allocation and addressing. The central objective of this method is the optimal use of embedded memories in the process of buffering data on-chip for an RVTPS operation. The developed software tool is an environment for generating HDL codes implementing the memory sub-components.</p><p>The tool integrates with the Interface and Memory Modelling (IMEM) tools in such a way that the IMEM’s output - the memory requirements of a RTVPS - is imported and processed in order to generate the HDL codes. IMEM is based on the philosophy that the memory requirements of an RTVPS can be modelled and synthesized separately from the development of the core RTVPS algorithm thus freeing the designer to focus on the development of the algorithm while relying on IMEM for the implementation of memory sub-components.</p> / Sensible Things That Communicate

<p>Abstract</p><p>Abstract The reason to measure the ion current in a combustion engine is to extract combustion parameters in order to achieve closed loop control of the combustion i.e. control of the spark, fuel and air into the engine. By using the spark plug, in a spark-ignited engine, as a probe it is possible to measure the ion current.</p><p>The purpose with this thesis is to improve an existing ion current interface.</p><p>A ringing caused by the ignition coil will follow by the ion current signal. Now the need of energy in the spark increase. Since increased energy in the spark gives a longer burn time and a longer ringing the ringing will extend into the ion current signal. The problem with the old interface is that the ringing is not symmetrical which could cause problems when filtering the signal.</p><p>The aim of this thesis is to achieve a symmetrical ringing and a interface that can handle an ion current amplitude from 0,1µA to 1mA.</p>

<p>The complexity of wireless communication integrated circuits is increasing day by day due to the trend of multifunction and multistandard support. This has not only increased the production cost of these RFICs but the testing cost is also increased significantly, as much advanced test equipments and instruments are needed to carry out the sophisticated performance tests. To avoid this higher cost and to reduce the test time, the alternative is to perform on-chip test. .In RF transceivers, loopback is an on-chip test technique in which Tx signal, instead of radiating through antenna is fed to the Rx chain through a test attenuator (TA) during the test mode. A highly linear offset mixer is needed to implement this on-chip loopback test for these transceivers. The aim of this thesis work is to design a highly linear upconversion offset mixer for loopback test in CMOS technology. This mixer is designed for Bluetooth and GSM/EDGE standards.</p><p>Few highly linear mixer architectures were simulated in 0.35um AMS process using Cadence SpectreRF software. When compared with active mixers, passive mixer consumes no dc power and there is significant reduction in silicon area overhead. The thesis presents a highly linear passive mixer with very low conversion loss and noise figure. The mixer is designed in 0.13um AMS CMOS process for higher cut off frequency and improved conversion loss. Pre and Post layout simulation results of the designed mixer are presented.</p>