<p>Radio Astronomers demand for highly sensitive astronomical facility. Their demand is a radio telescope that can detect the weakest and deepest radio signal. To fulfill the demand of high sensitive telescope, an entirely new way of realizing a radio telescope is required. One of the most important components in the RF front end that determines the sensitivity of a radio telescope is the Low Noise Amplifier (LNA).</p><p>The project has the selected process technologies which was searched and about the different noise matching topologies, input matching topology, wide band noise and input matching topologies has discussed by the author to the requirement of LNA in Astronomical purposes.</p><p>In this report, the best process technology candidate was chosen apart from selected technology candidates to obtain the minimum noise temperature over broad range frequency upon the modern era of Astronomical LNAs.</p><p>The work was continued to design a single ended LNA to obtain desired transistor parameters while using different noise matching topologies, input matching topologies, wideband noise and input matching topologies to have an LNA achievement with the design goal.</p><p>Further two stage amplifier was implemented to obtain minimum noise temperature, good stability, high gain, good input and output reflection coefficient with less power consumption.</p>

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<p>In thesis a Digital Down Converter (DDC) for Long Term Evolution (LTE) signals is designed. The DDC shall be implemented in hardware in a Field Programmable Gate Array (FPGA). For an FPGA the desired operating speed is high. The purpose of this thesis is therefore to determine if it is possible to design such a system.</p><p> The proposed DDC design consists of an efficient quadrature demodulator and a data rate decimation system. The decimation system consists of a Cascaded Integrator Comb (CIC) filter and a compensating Finite Impulse Response (FIR) filer. It is shown how the CIC and FIR filter can be made parallel in order to increase the data rate while still maintaining the clock speed.</p><p>This thesis shows that it is possible to design an FPGA based DDC for LTE signals with a decimation factor of 13, running at 399.36 MHz. The estimated performance increase of FPGA based design compared to the software based design is 319 times. Since floating-point numbers is inefficient to implement in hardware, thesis uses integer filter coefficients. This introduced gain in the system. This shows that fixed-point filter coefficients is to prefer.</p> / <p>I den här uppsatsen utvecklas en digital nerkonverterare (DDC) för signaler inom Long Term Evolution (LTE). DDC:n skall implementeras i hårdvara i en Field Programmable Gate Array (FPGA). Den önskade datahastigheten är hög för en FPGA. Därför är syftet med denna uppsatts att undersöka om det är möjligt att implementera ett sådant system i en FPGA.</p><p>Den framtagna designen av en DDC består av en effektiv I/Q-demodulator och ett datahastighetsdecimeringssystem. Systemet för att minska datahastigheten består av ett Cascaded Integrator Comb-filter (CIC) och ett kompenserande Finite Impulse Response-filter (FIR). Det visas hur CIC- och FIR-filter kan parallelliseras för att öka datahastigheten medan klockhastigheten bibehålls.</p><p>Det visas att det är möjligt att designa en FPGA-baserad DDC för LTE-signeler, med en decimeringsfactor på 13, som kör med en hastighet på 399.36 MHz. Den uppskattade prestandaökningen för denna FPGA-baserade lösning i jämförelse med mjukvarubaserad design är 319 gånger. I den här uppsatsen användes heltalsfilterkoefficienter eftersom flyttal inte kan implementeras effektivt i hårdvara. Detta skapade dock en oönskad förstärkning i det totala systemet. Därför är så kallade fixpunktsdecimaltal att föredra.</p>

<p>In this thesis measurement systems for the purpose of characterization of radio frequency power amplifiers are studied. Methods to increase the speed, accuracy, bandwidth, as well as to reduce the sampling requirements and testing cost are presented. A method intended for signal shaping with respect to peak to-average ratio reduction and its effects-improvements on the radio frequency front-end performance is investigated.</p><p>A time domain measurement system intended for fast and accurate measurements and characterization of radio frequency power amplifiers is discussed. An automated, fast and accurate technique for power and frequency sweep measurements is presented. Multidimensional representation of measured figure of merits is evaluated for its importance on the production-testing phase of power amplifiers.</p><p>A technique to extend the digital bandwidth of a measurement system is discussed. It is based on the Zhu-Frank generalized sampling theorem which decreases the requirements on the sampling rate of the measurement system. Its application for power amplifiers behavioral modeling is discussed and evaluated experimentally.</p><p>A general method for designing multitone for the purpose of out-of-band characterization of nonlinear radio frequency modules using harmonic sampling is presented. It has an application with the validation of power amplifiers behavioral models in their out-of-band frequency spectral support when extracted from undersampled data.</p><p>A method for unfolding the frequency spectrum of undersampled wideband signals is presented. It is of high relevance to state-of-the-art radio frequency measurement systems which capture repetitive waveform based on a sampling rate that violates the Nyquist constraint. The method is presented in a compact form, it eliminates ambiguities caused by folded frequency spectra standing outside the Nyquist band, and is relevant for calibration matters.</p><p>A convex optimization reduction-based method of peaks-to-average ratio of orthogonal frequency division multiplexing signals is presented and experimentally validated for a wireless local area network system. Improvements on the radio frequency power amplifier level are investigated with respect to power added efficiency, output power, in-band and out-of-band errors. The influence of the power distribution in the excitation signal on power amplifier performance was evaluated.</p>

The advances in VLSI and packaging technologies enable us to integrate a whole system on a single chip (SoC) or on a package module. In these systems, analog/RF electronics, digital circuitries, and memories coexist. This new technology brings us new freedom for system integration as well as new challenges in system design and implementation. To fully utilize the benefits of these new hardware technologies, concurrent design of system, chip, and package is necessary. This research aims to explore the new design space and opportunities for System-on-Package (SoP), with special attention on radio and mixed-signal system applications. Global level system partitioning for SoC and SoP with cost-performance trade-off, concurrent chip and design for high-speed off-chip signaling, global clock distribution, and ultra wideband (UWB) radio module are two fields in this research. Cost-performance driven for mixed-signal system partitioning in early conceptual level design is first addressed in this thesis. We develop a modeling technique to pre-estimate the cost and performance. The performance model evaluates various noise isolation technologies, such as using guard rings, and partitioning the system into several chips. In cost analysis, new factors such as extra chip area and additional process steps due to mixed signal isolation, integration of intellectual property (IP) right module or “virtual components”, yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip are considered. An efficient computation algorithm, namely COMSI, is developed for cost estimation under various mixed-signal performance constraints. System interconnect topologies have been moving away from multi-point bus architecture and towards high-speed serial links. But low interaction between chip and package design has more and more limited system performance. We address concurrent chip and package design and co-optimization for high-speed off-chip signaling in this part. First we explore the interconnect and package constraints to the circuit and system architecture. Proper equivalent circuit models for package parasitics are set up and then a 3-dimension electromagnetic (EM) solver is used to extract the parasitic parameters of package. After that, bandwidth and noise of the signal channel are estimated. The optimal off-chip singling is designed according to these packages and interconnection constraints. We also analyzed the global clock distribution using co-design method. We developed a low cost, low power consumption, and low complexity UWB radio module using co-design method and SoP technologies. The module will be used in low data rate and long-range wireless intelligent systems such as radio frequency identification (RFID) or wireless sensors networks (WSN). Liquid-crystal-polymer (LCP) based SoP technologies were used to implement the module. / <p>QC 20101006</p>

In line with the quality awareness of good prevention of pressure sores and in treatment of those sores already developed, evaluation of antidecubitus mattresses plays an important role. However, there are shortages in the evaluations performed today, since often interface pressure is the only parameter regarded. Since ischaemia in the tissue is the primary cause of pressure sore, the focus in this thesis is on blood flow measurements in tissue exposed external loading. To study the tissue blood flow would give a better and more direct indication on the mattress effectiveness in minimizing the negative effects on the tissue viability. The results presented in this thesis reveal that the superficial blood flow in areas prone to pressure sore development, is affected by increased skin temperature and external loading of the tissue. Both the effects from pressure and shear stress have been studied. Measurements of the tissue blood flow is interesting to relate to the two theories about at which tissue layer the pressure sores start to develop. To achieved more knowledge about the pressure sore etiology and also be able to non-invasively measure the tissue blood flow for evaluations of antidecubitus mattresses an optical sensor has been developed. The sensor combines the two optical methods, laser Doppler flowmetry and photoplethysmography. With the design of the sensor, measurements of the superficial skin blood flow and the deeper blood flow, even the muscle blood flow, can be performed. Measurement depths of 2 mm, 8 mm, and 20 mm into the tissue is assumed. Preliminary result from measurements performed with the optical sensor in four test subjects, revealed great individual differences in blood flow, but also different response to the same external loading at different measurement depths, in the same individual. This new optical sensor is likely to be of great value in future studies of pressure sore etiology and in future evaluations of antidecubitus mattresses.

In this thesis, both a method and a tool to enable efficient memory synthesis for real-time video processing systems on field programmable logic array are presented. In real-time video processing system (RTVPS), a set of operations are repetitively performed on every image frame in a video stream. These operations are usually computationally intensive and, depending on the video resolution, can also be very data transfer dominated. These operations, which often require data from several consecutive frames and many rows of data within each frame, must be performed accurately and under real-time constraints as the results greatly affect the accuracy of application. Application domains of these systems include object recognition, object tracking and surveillance. Developments in field programmable gate array (FPGA) have been the motivation for choosing them as the platform for implementing RTVPS. Essential logic resources required in RTVPS operation are currently available optimized and embedded in modern FPGAs. One such resource is the embedded memory used for data buffering during real-time video processing. Each data buffer corresponds to a row of pixels in a video frame, which is allocated using a synthesis tool that performs the mapping of buffers to embedded memories. This approach has been investigated and proven to be inefficient. An efficient alternative employing resource sharing and allocation width pipelining will be discussed in this thesis. A method for the optimal use of these embedded memories and, additionally, a tool supporting automatic generation of hardware descriptions language (HDL) codes for the synthesis of the memories according to the developed method are the main focus of this thesis. This method consists of the memory architecture, allocation and addressing. The central objective of this method is the optimal use of embedded memories in the process of buffering data on-chip for an RVTPS operation. The developed software tool is an environment for generating HDL codes implementing the memory sub-components. The tool integrates with the Interface and Memory Modelling (IMEM) tools in such a way that the IMEM’s output - the memory requirements of a RTVPS - is imported and processed in order to generate the HDL codes. IMEM is based on the philosophy that the memory requirements of an RTVPS can be modelled and synthesized separately from the development of the core RTVPS algorithm thus freeing the designer to focus on the development of the algorithm while relying on IMEM for the implementation of memory sub-components. / Sensible Things That Communicate

In this thesis, digit-serial implementation of recursive digital filters is considered. The theories presented can be applied to any recursive digital filter, and in this thesis we study the lossless discrete integrator (LDI) allpass filter. A brief introduction regarding suppression of limit cycles at finite wordlength conditions is given, and an extended stability region, where the second-order LDI allpass filter is free from quantization limit cycles, is presented. The realization of digit-serial processing elements, i.e., digit-serial adders and multipliers, is studied. A new digit-serial hybrid adder (DSHA) is presented. The adder can be pipelined to the bit level with a short arithmetic critical path, which makes it well suited when implementing high-throughput recursive digital filters. Two digit-serial multipliers which can be pipelined to the bit level are considered. It is concluded that a digit-serial/parallelmultiplier based on shift-accumulation(DSAAM) is a good candidate when implementing recursive digital systems, mainly due to low latency. Furthermore, our study shows that low latency will lead to higher throughput and lower power consumption. Scheduling of recursive digit-serial algorithms is studied. It is concluded that implementation issues such as latency and arithmetic critical path are usually required before scheduling considerations can be made. Cyclic scheduling using digit-serial arithmetics is also considered. It is shown that digit-serial cyclic scheduling is very attractive for high-throughput implementations.

Thanks to its ability to generate a stable yet programmable output frequency, Phase Locked Loop (PLL) frequency synthesizers are found in most modern radio transceivers. All practical PLL implementations suffer from unwanted frequency components such as phasenoise and spurious tones, and since these components affect system performance they must be predicted and minimized. This thesis discuss the design and implementation of fully integrated PLL circuits. Techniques to predict system performance are investigated. The strongly non-linear operation of PLL building blocks are analyzed, using both analytical and numerical methods. Techniques to reduce impact of interferer down-conversion and noise folding are suggested. Methods to perform automatic calibration in order to make circuits less sensitive to process variations are proposed. The techniques are verified through a number of PLL implementations. The design and implementation of a transceiver targeting a dual band IEEE 802.11 a/b/g wireless LAN operation is discussed. The circuit use two PLL:s operating at 1310 to 1510 MHz and 3.84 GHz respectively. Noise contributions of various PLL building blocks and their impact on over all system performance are analyzed. The combined integrated phase noise is below -34 dBc, and measured transceiver Error Vector Magnitude (EVM) is better than 2.5 dB in both the 2.4 and 5 GHz bands. A low power frequency synthesizer targeting Frequency Shift Keying applications such as ZigBee and BlueTooth is presented. The synthesizer use open-loop direct modulation of the carrier, but unlike conventional implementations, the proposed synthesizer is open both when transmitting and receiving data. This allows the use of a small area on-chip loop filter without violating noise or spurious requirements. To handle the frequency drift normally associated with open-loop implementations, a low-leakage charge-pump is proposed. The synthesizer is implemented using a 0.18μm CMOS process. Total power consumption is 9 mW and the circuit area including the VCO inductors and on-chip loopfilter is 0.32mm2. Measured leakage current is less than 2 fA. A small area amplitude detector circuit is proposed. The wide-band operation and small input capacitance make the circuit suitable for embedding in an RF system on-chip, allowing measurement of on-chip signal levels and automatic calibration. Finally an oscillator topology reducing the phase noise in voltage controlled oscillators is suggested. By using on-chip decoupling and an amplitude control circuit to adjust oscillator bias, the impact of current source noise is eliminated. The theoretical phase noise is reduced 3.9 dB compared to a conventional LC oscillator using the same bias current. / QC 20100817