<p> Embedded deterministic test (EDT) is a manufacturing test paradigm that combines the compression advantage of built-in self-test with the high fault coverage of deterministic stimuli inherent to methods based on automatic test pattern generation and external testers. Despite enabling the use of low cost testers for rapidly achieving high fault coverage, EDT must consciously use the available tester channels to ensure non-disruptive scaling to future devices of increased complexity. The focus of this thesis is to introduce a new EDT approach for systems-on-a-chip (SOCs) that are designed using embedded cores that are intellectual property (IP)-protected.</p> <p> Following an introduction to integrated circuit testing and an overview of the related work, we define the criteria that must be satisfied by the EDT approaches for the future SOCs of ever growing complexity. Then we observe that the necessary amount of compressed volume of test data transferred from the tester to the embedded cores in an SOC varies significantly during the testing process. This motivates a novel approach to compressed SOC testing based on time-multiplexing the tester channels. It is shown how the introduction of test control channels will reduce the number of required test data channels which will then have increased usage, as the embedded cores will receive compressed test data only when necessary. Through the use of modular and scalable hardware for on-chip test control and test data decompression, we define a new algorithmic framework for test data compression that is applicable to SOCs comprising IP-protected blocks. Experimental results indicate that our approach compares to the existing approaches for EDT that have similar design criteria and methodology constraints, while providing a seamless integration to low cost test equipment.</p> / Thesis / Master of Applied Science (MASc)

Since its inception in the nineteenth century, the Internal Combustion Engine (ICE) remains the most prevalent technology in transportation systems to date. In order to minimize emissions, it is important that ICE is operated according to its optimized design conditions. As such, condition monitoring and Fault Detection and Diagnosis (FDD) tools can play an important role in detecting conditions that would affect the operability of the engine. In this research, different signal-based Fault Detection and Diagnosis (FDD) techniques are researched and implemented for fault condition monitoring of ICE. The implementation of prognostics for the engine in an automated form has important consequences that include cost savings, increased reliability, reduction of GHG emissions, better safety, and extended life for the vehicle. In this research, in order to carry out FDD onboard, a low-cost and flexible internet-based data-acquisition system (DAQ) was designed and implemented. The main part of the system is an embedded hardware running a full desktop version of Linux. This sensory system leverages the positive aspects of both real-time and general-purpose architectures to ensure engine monitoring at high sampling rates. Unlike other commercial DAQ systems, the software of this device is open-source, free of charge, and highly expandable to suit other FDD applications. In addition to data collection at high sampling rates, the FDD system includes advanced FDD strategies. The Fault Detection and Diagnosis strategies considered use a combination of Fourier Transforms (FT), Wavelet Transforms (WT), and Principal Component Analysis (PCA). Meanwhile, Fault Classification was carried using Neural Networks consisting of the Multi-Layer Perceptron (MLP). Three strategies were comparatively considered for the training of the Neural Network (NN), namely the Levenberg-Marquardt (LM), the Extended Kalman Filter (EKF), and the Smooth Variable Structure Filter (SVSF) techniques. The proposed FDD system was able to achieve 100% accuracy in classifying a set of engine faults. / Thesis / Master of Applied Science (MASc)

The high-voltage SiC power semiconductor devices have been developed in recent years. They cause an urgent in the need for the power semiconductor packaging to have not only low interconnect resistance, less noise, less parasitic oscillations, improved reliability, and better thermal management, but also High-Voltage (HV) blocking capability. The existing power semiconductor packaging technologies includes wire-bonding interconnect, press pack, flip-chip technology, metal posts interconnected parallel plates structure (MIPPS), dimple array interconnection (DAI), power overlay (POL) technology, and embedded power (EP) technology. None of them meets the requirements of low profile and high voltage rating. The objective of the work in this dissertation is to propose and design a high-voltage power semiconductor device packaging method with low electric field stress and low profile to meet the requirments of high-voltage blocking capability. The main contributions of the work presented in this dissertation are: 1. Understanding the electric field distribution in the package. The power semiconductor packaging is simulated by using Finite Element Analysis (FEA) software. The electric field distribution is known and the locations of high electric field concentration are identified. 2. Development of planar high-voltage power semiconductor device packaging method With the proposed structure in the dissertation, the electric field distribution of a planar device package is improved and the high electric field intensity is relieved. 3. Development of design guidelines for the propsed planar high-voltage device packaging method. The influence of the structure dimensions and the material properties is studied. An optimal design is identified. The design guideline is given. 4. Fabrication and experimental verification of the proposed high-voltage device packaging method A detailed fabrication procedure which follows the design guideline is presented. The fabricated modules are tested by using a high power curve tracer. Test results verify the proposed method. 5. Simplification of the structure model of the proposed device package The package structure model is simplified through the elimination of power semiconductor device internal structure model. The simplified model can be simulated by a non-power device simulator. The simulation results of the simplified model match the simulation results of the complete model very well. / Ph. D.

The huge advancement in the textiles industry and the accurate control on the mechanization process coupled with cost-effective manufacturing offer an innovative environment for new electronic systems, namely electronic textiles. The abundance of fabrics in our regular life offers immense possibilities for electronic integration both in wearable and large-scale applications. Augmenting this technology with a set of precepts and a simulation environment creates a new software/hardware architecture with widely useful implementations in wearable and large-area computational systems. The software environment acts as a functional modeling and testing platform, providing estimates of design metrics such as power consumption. The construction of an electronic textile (e-textile) hardware prototype, a large-scale acoustic beamformer, provides a basis for the simulator and offers experience in building these systems. The contributions of this research focus on defining the electronic textile architecture, creating a simulation environment, defining a networking scheme, and implementing hardware prototypes. / Ph. D.

This thesis presents the design and evaluation of an operating system kernel specially designed for dataflow software. Dataflow is a style of software architecture that is well suited for control and "signal flow" applications. This architecture involves many small processes and lots of inter-process communication, which impose too much overhead on traditional RTOSes. This thesis describes design and implementation of the Dataflow Architecture Real-time Kernel (DARK). DARK is a reconfigurable, multithreaded and preemptive operating system kernel that introduces a special data-driven scheduling strategy for dataflow applications. It uses the underlying hardware for high-speed context switching between the kernel and applications, which is five times faster than the ordinary context switch. The features of the kernel can be configured according to performance requirements without change to the applications. Along with the performance evaluation of DARK, the performance comparison results of DARK with two commercial RTOSes: MicroC/OS-II and Analog Devices VDK++ are also provided. / Master of Science

This thesis presents the design and evaluation of an object-oriented (OO) operating system kernel for real-time embedded systems based on dataflow architecture. Dataflow is a software architecture that is well suited to applications that involve signal flows and value transformations. Typically, these systems comprise numerous processes with heavy inter-process communications. The dataflow style has been adopted for the control software for PEBB (Power Electronic Building Block) systems by the Center for Power Electronic Systems (CPES), Virginia Tech., which is involved in a research effort to modularize and standardize power electronic components. The goal of our research is to design and implement an efficient object-oriented kernel for the PEBB system and compare its performance vis-à-vis that of a non-OO kernel. It presents strategies for efficient OO design and a discussion of how OO performance issues can be ameliorated. We conclude the thesis with an evaluation of the advantages gained by using the OO paradigm both from the standpoint of the classically cited advantages of OO programming and other crucial aspects. / Master of Science

The research conducted was sponsored by JVI of Pittsfield, Massachusetts. JVI has developed a steel embedded connection, referred to as a shooter. The shooter is provided in capacities, a 40 kip capacity shooter and a 50 kip capacity shooter. This steel connection is embedded near the end of a double-tee prestressed girder. Double-tee prestressed girders are a primary component used in the construction of parking garages. Typical double-tee lengths are 60 to 75 feet; however, for this research 20 ft long segments were cast and tested with the shooter installed. This project had three main goals. The first goal was to develop a preliminary design for the reinforcement around the shooter and test the shooters' capacity in the laboratory to determine if the stated capacity was correct. Four different designs were created, two designs for the 40 kip capacity shooter and 2 designs for the 50 kip capacity shooter. Each design was placed in one stem of the double-tee and tested at the laboratory. Results from these tests indicate that that each specimen achieved the stated capacity. However, failure was not a connection failure but a shear bond failure. The second goal was to take the information gathered from testing and develop a design model that could be used for other situations for this type of connection. The design model was created according to the guidelines in the ACI 318-08 code. Two different methods were used, a strut-and-tie model and a modified ACI code approach. From these designs it was determined that the strut-and-tie model should be used for the design of these connections; however, more research needs to be done before using the modified ACI code approach. The final goal was to determine if finite element analysis could be used to determine if the load at which large cracks that immediately proceed failure occur could be predicted. From this analysis it was determined that a load range could be predicted in which a crack could form as well as a range of what the transfer length of the strands could be. / Master of Science

Micro gas chromatography (μGC) system is a miniaturized and portable version of the conventional GC system, suitable for various applications such as healthcare and environmental analysis. The process of gas chromatography requires precise temperature control for the micro-fabricated preconcentrators and separation columns used since temperature changes directly affect retention time. Proportional Integral and Derivative (PID) controllers provide reliable temperature control and can be tuned to obtain the desired response. The conventional method of tuning the PID control parameters by trial and error is a tedious process and time-consuming process. This thesis aims to develop a PID auto-tuning and control system for auto-tuning microfabricated heaters in modular μGC systems. The developed system is based on the Ziegler Nichols rule-based PID tuning method for closed-loop systems, which uses the relay response of the micro-heater to calculate the PID tuning parameters. The system also includes an analysis system to verify the performance of the PID-tuned values and a tuning system where the PID values can be further tuned to obtain more precise control for the heaters. The aim of developing this system is to reduce the effective tuning time for heaters while satisfying the control requirements. In this thesis, we discuss the tuning methodology and the implementation of the PID tuning and control system, followed by a performance evaluation of the heaters tuned using the proposed system is discussed. / Master of Science / Gas chromatography (GC) is an established technique used for the qualitative and quantitative analysis of compounds present in a mixture. Micro-gas chromatography (μGC) systems are miniaturized versions of conventional GC systems. They are portable, energy-efficient, and facilitate on-site analysis in real-time, which is suitable for applications such as health care, forensics, and environmental analysis, requiring in-field analysis. GC is based on the principle that components of a gaseous mixture, when passed through a heated column coated with a stationary phase, separate out based on their extent of interaction with the stationary phase. The temperature control needs to be precise since it directly affects the process. PID control is the most common and reliable method for temperature control. It can be tuned to obtain the desired response, which can, however, be a tedious process. This thesis aims to develop a PID auto-tuning and control system for μ-fabricated heaters in μGC systems. As a part of this thesis, a system facilitating faster tuning of PID parameters for a given heater using the Ziegler Nichols closed-loop tuning method is developed. It uses the relay response of the micro-heater to determine the tuning value. The obtained PID values can be evaluated using the analysis system developed as a part of the system and can be further fine-tuned using the provided system to obtain the desired response. As a part of this thesis, we first discuss the development of the PID tuning and control system, after which the performance of the tuned values is evaluated for two micro-heaters.

Embedded systems for humanoid robots are required to be reliable, low in cost, scalable and robust. Most of the applications related to humanoid robots require efficient force control of Series Elastic Actuators (SEA). These control loops often introduce precise timing requirements due to the safety critical nature of the underlying hardware. Also the motor controller needs to run fast and interface with several sensors. The commercially available motor controllers generally do not satisfy all the requirements of speed, reliability, ease of use and small size. This work presents a custom motor controller, which can be used for real time force control of SEA on humanoid robots and exoskeletons. Emphasis has been laid on designing a system which is scalable, easy to use and robust. The hardware and software architecture for control has been presented along with the results obtained on a novel Series Elastic Actuator based humanoid robot THOR. / Master of Science / Humanoid robots can be used in several applications such as disaster management, replacing manual work in hazardous environments, helping human beings in navigation and day to day activities, etc. This increase in interests in humanoid robotics and related research in exoskeletons has led to the need of reliable embedded systems which is used to control the machines. These embedded systems are often required to be low in cost, scalable and robust. The specification required from the electronics and the embedded systems vary based on the robot’s capabilities. Also, there is a gap between the requirements of humanoid robots in research and in industrial setting. This work focuses on bridging the gap by proposing a solution which is semi-custom, low in cost, reliable and scalable. The work has been shown to perform as expected on the stat-of-art humanoid robot THOR which was built at Virginia Tech. Using the proposed design technique can not only deliver good performance but can also act as a quick prototyping tool for other robotics projects related to humanoid robotics and exoskeletons.

This dissertation introduces Power Fingerprinting (PFP), a novel technique for assessing the execution integrity of embedded devices. A PFP monitor is an external device that captures the dynamic power consumption of a processor using fine-grained measurements at the clock-cycle level and applies anomaly detection techniques to determine whether the integrity of the system has been compromised. PFP uses a set of trusted signatures from the target code that are extracted during a pre-characterization process. PFP provides significant visibility into the internal execution status, making it extremely robust against evasion. Because of its independence and physical separation, PFP prevents attacks on the monitor itself and introduces minimal overhead on platforms with resource constraints. Due to its anomaly detection operation, PFP is effective against unknown (zero-day) attacks. This dissertation demonstrates the feasibility of PFP on different platforms with different configurations and architectural complexities. Experimental results demonstrate the feasibility of PFP in a basic deterministic embedded platform for radio applications in two different areas: security and regulatory certification. For more complex, non-deterministic platforms, this works presents feasibility results for monitoring the execution integrity of complex software on a high-performance Android platform, including the ability to detect a real privilege escalation attack. In addition, the dissertation develops several general techniques to implement and integrate PFP into embedded platforms such as a general monitoring architecture, a methodology to characterize software modules and extract signatures, and an approach to perform board characterization and improve monitoring sensitivity. / Ph. D.